Juha Plosila
Head of the Robotics and Autonomous Systems Unit
juplos@utu.fi +358 29 450 2621 +358 50 383 9453 Vesilinnantie 5 Turku |
autonomous systems; robotics; unmanned vehicles; drones; embedded systems; cyber physical systems; internet of things; smart systems; fog/edge computing; multi-agent systems; multiprocessors; network on chip; system on chip; multiprocessor system on chip; chip multiprocessors; heterogeneous systems; reconfigurable computing; digital circuits and systems; formal methods
Autonomous Systems Laboratory (ASL): https://asl.utu.fi/
Dr. Juha Plosila (born 1965) is Professor (full) in autonomous systems and robotics and the head of the Autonomous Systems Laboratory (ASL) research group (https://asl.utu.fi/) and Smart Systems (formerly Embedded Electronics) cost centre at the University of Turku (UTU) Department of Computing (formerly Department of Future Technologies) since 2019. He received his PhD in electronics and communication technology from UTU in 1999 and his Adjunct Professor (Docent) title in digital systems design in 2006. He held a 5-year position of Academy Research Fellow (Academy of Finland) in 2006-2011 and served as a senior University Lecturer in embedded computing at UTU in 2011-2018. During his tenure at UTU since 2000, he has led many externally funded research projects, supervised more than 20 PhD theses, and served in the management committees of several master's programmes. Plosila has been an active participant in the European Institute of Innovation and Technology (EIT) knowledge and innovation community EIT Digital since 2011, leading the EIT Digital Master Programme in Embedded Systems (a European double-degree programme with 6 partner universities) and representing UTU in the EIT Digital Finland Node Strategy Committee.
Plosila's current research interests include intelligent adaptive and reconfigurable multi-processing platforms, self-aware multi-agent monitoring and control, machine-learning and optimization, as well as application of heterogeneous energy efficient architectures to new computational challenges in the areas of cyber-physical systems and internet-of-things, with a special focus on autonomous multi-robot systems and fog/edge computing. He also has a strong background in network-on-chip design and formal mehods for system design and verification.
Google Scholar statistics: https://scholar.google.com/citations?user=em4kCrUAAAAJ&hl=en
Lecturer for 18 different courses since 1999 in the fields of digital circuit and system design, multiprocessor architectures, computer architectures, reconfigurable computing, embedded systems, modelling and verification, as well as autonomous systems:
Autonomous Systems Architectures, MSc-level, 5 ECTS (2019- ); Regonfigurable Computing, MSc-level, 5 ECTS (at Fudan University, China, 2013- ); Processor Architectures, BSc-level, 5 ECTS (2020); Computer Architectures and Operating Systems, BSc-level, 4 ECTS (2017-2019), Multiprocessor Architectures, MSc-level, 5 ECTS, (2006, -08, -10, 2012-2018); System on Chip Design, MSc-level, 5 ECTS (2015-2016); Seminar on Embedded Computing, MSc/PhD-level, 5 ECTS (2012-2014); Modelling Parallel Systems, MSc-level (2011); Formal System Modelling and Verification, MSc-level, 5 ECTS, (2008, -10); Post Graduate Course on Digital Circuit & System Design, PhD-level; 5 ECTS (2009); Advanced Multiprocessor Systems, MSc-level, 5 ECTS (2009); System Verification, MSc-level, 5 ECTS (2007); Computer Architectures, BSc-level, 7 ECTS (2006-2007); Asynchronous System Design, MSc-level, 5 ECTS (2003, -05, -07); Formal System Specification and Design, MSc-level; 10 ECTS (2004, -06); Digital Integrated Circuit Design, BSc-level, 7 ECTS (2000-2005); Digital Systems Engineering, MSc-level, 10 ECTS (2001, -02, -04); Principles of Digital Design, BSc-level, 5 ECTS (1999-2000, -04).
- Self-Timed Thermal Sensing and Monitoring of Multicore Systems (2009) 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Vaddina KR, Nigussie E, Liljeberg P, Plosila J
- A novel hardware acceleration scheme for Java method calls (2008)
- IEEE International Symposium on Circuits and Systems. Proceedings
- AREA EFFICIENT DELAY-INSENSITIVE AND DIFFERENTIAL CURRENT SENSING ON-CHIP INTERCONNECT (2008) Proceedings of 2008 IEEE International SOC Conference Nigussie E, Plosila J, Isoaho J
- Distributed Traffic Monitoring Methods for Adaptive Network-on-Chip (2008) NORCHIP Ville Rantala, Teijo Lehtonen, Pasi Liljeberg, Juha Plosila
- Current mode on-chip interconnect using level-encoded two-phase dual-rail encoding (2007)
- IEEE International Symposium on Circuits and Systems. Proceedings
- Fault tolerance analysis of NoC architectures (2007)
- IEEE International Symposium on Circuits and Systems. Proceedings
- High-performance long NoC link using delay-insensitive current-mode signaling (2007) Ethiopia Nigussie, Teijo Lehtonen, Sampo Tuuna, Juha Plosila, Jouni Isoaho
- Analysis of crosstalk and process variations effects on on-chip interconnects (2006) Proceedings of 2006 International Symposium on System-on-Chip Nigussie E, Tuuna S, Plosila J, Isoaho J
- An approach for analysing and improving fault tolerance in radio architectures (2006)
- IEEE International Symposium on Circuits and Systems. Proceedings
- Comparative study of synthesis for asynchronous and synchronous cache controllers (2006) Norchip Conference, 2006. 24th Tuominen J, Santti T, Plosila J
- Comparative study of synthesis for asynchronous and synchronous cache controllers (2006) Proceedings of the 24th IEEE Norchip Conference Tuominen J, Santti T, Plosila J
- Delay-insensitive on-chip communication link using low-swing simultaneous bidirectional signaling (2006) Proceedings: IEEE Computer Society Annual Sysmposium on VLSI 2006: Emerging VLSI Technologies and Architectures Nigussie E, Plosila J, Isoaho J
- Fault-tolerant routing approach for reconfigurable networks-on-chip (2006)
- International Symposium on System-on-Chip
- Full-duplex link implementation using dual-rail encoding and multiple-valued current-mode logic (2006)
- IEEE International Symposium on Circuits and Systems. Proceedings
- Network on chip routing algorithms (2006) Ville Rantala, Teijo Lehtonen, Juha Plosila
- Architecture for an advanced Java co-processor (2005) International Symposium on Signals, Circuits & Systems, ISSCS 2005 Santti T, Plosila J
- Instruction folding for an asynchronous Java co-processor (2005) System-on-Chip, 2005. Proceedings. 2005 International Symposium on Santti T, Plosila J
- Instruction folding for an asynchronous Java co-processor (2005) International Symposium of System-on-Chip Santti T, Plosila J
- On asynchronous full-duplex dual-rail link with multiple-valued current-mode signaling (2005) NORCHIP Proceeding Nigussie E, Plosila J, Isoaho J
- Real time flow control for an advanced Java co-processor (2005) Proceeding of IEEE 23rd Norchip Conference Santti T, Plosila J
