A novel hardware acceleration scheme for Java method calls

: Santti T, Tyystjarvi J, Plosila J

: N/A

: 2008

IEEE International Symposium on Circuits and Systems. Proceedings

: IEEE International Symposium on Circuits and Systems

PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10

: IEEE INT SYMP CIRC S

: 1676

: 1679

: 4

: 978-1-4244-2078-0

: 0271-4302

DOI: https://doi.org/10.1109/ISCAS.2008.4541758

This paper presents a novel strategy for accelerating the method calls in the REALJava co-processor. The hardware assisted virtual machine architecture is described shortly to provide context for the method call acceleration. The strategy is realized as an FPGA prototype. It allows measurements of real life performance increase, and validates the concept. The system is intended to be used in embedded environments, limiting the CPU performance and memory available to the virtual machine. The co-processor is designed in a highly modular fashion, especially separating the communication from the actual core. This modularity of the design makes the co-processor more reusable and allows system level scalability. This work is a part of a project focusing on design of an advanced Java co-processor for Java intensive SoC applications.