Fault-tolerant routing approach for reconfigurable networks-on-chip

: Rantala P, Lehtonen T, Isoaho J, Plosila J

: 2006

International Symposium on System-on-Chip

: International Symposium on System-on-Chip 2006

2006 International Symposium on System-on-Chip Proceedings

: 107

: 110

: 4

: 978-1-4244-0621-0

We introduce fault-tolerant on-chip routing philosophy for two-dimensional meshes. It is an extension to the concept of packet connected circuit, PCC. In order to increase reliability we have designed an automatic rerouting property to a single switch node and added return channel to the communication route. An autonomic routing switch node is modeled asynchronously and implemented using Haste language. The logical functionality of routing is illustrated as a single study case in 7*8 mesh. The routing success is further analyzed in congesting and faulty environment.