Juha Plosila
Head of the Robotics and Autonomous Systems Unit
juplos@utu.fi +358 29 450 2621 +358 50 383 9453 Vesilinnantie 5 Turku ORCID-tunniste: https://orcid.org/0000-0003-4018-5495 |
autonomous systems; robotics; unmanned vehicles; drones; embedded systems; cyber physical systems; internet of things; smart systems; fog/edge computing; multi-agent systems; multiprocessors; network on chip; system on chip; multiprocessor system on chip; chip multiprocessors; heterogeneous systems; reconfigurable computing; digital circuits and systems; formal methods
Autonomous Systems Laboratory (ASL): https://asl.utu.fi/
Dr. Juha Plosila (born 1965) is Professor (full) in robotics and autonomous systems, Head of the Robotics and Autonomous Systems unit (cost centre), and Co-Lead of the Autonomous Systems Laboratory (ASL) research group (https://asl.utu.fi/) at the Department of Computing, Universitity of Turku. He received his PhD in electronics and communication technology from UTU in 1999 and his Adjunct Professor (Docent) title in digital systems design in 2006. He held a 5-year position of Academy Research Fellow (Academy of Finland) in 2006-2011 and served as a senior University Lecturer in embedded computing at UTU in 2011-2018. During his tenure at UTU since 2000, he has led many externally funded research projects, supervised more than 20 PhD theses, and served in the management committees of several master's programmes. Plosila has been an active participant in the European Institute of Innovation and Technology (EIT) knowledge and innovation community EIT Digital since 2011, leading the EIT Digital Master Programme in Embedded Systems (a European double-degree programme with 6 partner universities) and representing UTU in the EIT Digital Finland Node Strategy Committee.
Plosila's current research focuses on methodologies for the analysis, design, and control of networked autonomous systems, including different types of intelligent robotic systems as well as adaptive AI systems for runtime resource management in embedded and distributed computing. This combines expertise in the areas of robotics, multi-agent systems, optimisation, machine learning, computer vision, and computing systems design. He also has a strong background in network-on-chip design as well as in formal mehods for system design and verification.
Google Scholar statistics: https://scholar.google.com/citations?user=em4kCrUAAAAJ&hl=en
Lecturer for 18 different courses since 1999 in the fields of digital circuit and system design, multiprocessor architectures, computer architectures, reconfigurable computing, embedded systems, modelling and verification, as well as autonomous systems:
Autonomous Systems Architectures, MSc-level, 5 ECTS (2019- ); Regonfigurable Computing, MSc-level, 5 ECTS (at Fudan University, China, 2013- ); Processor Architectures, BSc-level, 5 ECTS (2020); Computer Architectures and Operating Systems, BSc-level, 4 ECTS (2017-2019), Multiprocessor Architectures, MSc-level, 5 ECTS, (2006, -08, -10, 2012-2018); System on Chip Design, MSc-level, 5 ECTS (2015-2016); Seminar on Embedded Computing, MSc/PhD-level, 5 ECTS (2012-2014); Modelling Parallel Systems, MSc-level (2011); Formal System Modelling and Verification, MSc-level, 5 ECTS, (2008, -10); Post Graduate Course on Digital Circuit & System Design, PhD-level; 5 ECTS (2009); Advanced Multiprocessor Systems, MSc-level, 5 ECTS (2009); System Verification, MSc-level, 5 ECTS (2007); Computer Architectures, BSc-level, 7 ECTS (2006-2007); Asynchronous System Design, MSc-level, 5 ECTS (2003, -05, -07); Formal System Specification and Design, MSc-level; 10 ECTS (2004, -06); Digital Integrated Circuit Design, BSc-level, 7 ECTS (2000-2005); Digital Systems Engineering, MSc-level, 10 ECTS (2001, -02, -04); Principles of Digital Design, BSc-level, 5 ECTS (1999-2000, -04).
- Process Variation Tolerant On-Chip Communication Using Receiver and Driver Reconfiguration (2010) 11th IEEE International Symposium on Quality Electronic Design Nigussie E, Plosila J, Isoaho J
(A4 Vertaisarvioitu artikkeli konferenssijulkaisussa) - Research and Practices on 3D Networks-on-Chip Architectures (2010) Proc. of IEEE International Norchip Conference (NORCHIP’10) Rahmani A-M, Latif K, Liljeberg P, Plosila J, Tenhunen H
(A4 Vertaisarvioitu artikkeli konferenssijulkaisussa) - Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects (2010)
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
(A1 Vertaisarvioitu alkuperäisartikkeli tieteellisessä lehdessä ) - Thermal Modelling of 3D Multicore Systems in a Flip-Chip Package (2010) IEEE International SoC Conference (SoCC 2010) Vaddina K R, Mitra T, Liljeberg P, Plosila J
(A4 Vertaisarvioitu artikkeli konferenssijulkaisussa) - Tree-Model Based Mapping for Energy-Efficient and Low-Latency Network-on-Chip (2010) Proceedings of 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Yang B, Xu T C, Säntti T, Plosila J
(A4 Vertaisarvioitu artikkeli konferenssijulkaisussa) - Efficient Execution of Switch Instructions on a Multicore Java Co-Processor System (2009) IEEE TECHPOS 2009 Tyystjarvi J, Santti T, Plosila J
(A4 Vertaisarvioitu artikkeli konferenssijulkaisussa) - Fansi: Fault tolerant Network-on-Chip simulator (2009) Teijo Lehtonen, Ville Rantala, Pasi Liljeberg, Juha Plosila
(D4 Julkaistu kehittämis- tai tutkimusraportti tai -selvitys ) - Fault Tolerant Distributed Routing Algorithms for Mesh Networks-on-Chip (2009) 9th International Symposium on Signals, Circuits and Systems, ISSCS 2009 Lehtonen T, Liljeberg P, Plosila J
(A4 Vertaisarvioitu artikkeli konferenssijulkaisussa) - High-speed completion detection for current sensing on-chip interconnects (2009)
- Electronics Letters
(A1 Vertaisarvioitu alkuperäisartikkeli tieteellisessä lehdessä ) - Multi Network Interface Architectures for Fault Tolerant Network-on-Chip (2009) 9th International Symposium on Signals, Circuits and Systems, ISSCS 2009 Rantala V, Lehtonen T, Liljeberg P, Plosila J
(A4 Vertaisarvioitu artikkeli konferenssijulkaisussa)
