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High-speed completion detection for current sensing on-chip interconnects
Tekijät: Nigussie E, Plosila J, Isoaho J
Kustantaja: INST ENGINEERING TECHNOLOGY-IET
Julkaisuvuosi: 2009
Journal: Electronics Letters
Tietokannassa oleva lehden nimi: ELECTRONICS LETTERS
Lehden akronyymi: ELECTRON LETT
Vuosikerta: 45
Numero: 11
Aloitussivu: 547
Lopetussivu: 548
Sivujen määrä: 2
ISSN: 0013-5194
DOI: https://doi.org/10.1049/el.2009.0403
Tiivistelmä
A novel completion detection technique for delay insensitive current sensing on-chip interconnects is presented. The scheme is based on sensing currents on the data wires and comparing the sum of these currents to an appropriately set reference. The goal is to solve the performance bottleneck caused by conventional voltage-mode detection methods. With the channel width of 64 bits, the proposed method is 4.65 times faster and takes 36% less area than the voltage-mode scheme. Furthermore, its speed does not degrade when increasing the channel bit width. It is implemented in a 65 nm CMOS technology.
A novel completion detection technique for delay insensitive current sensing on-chip interconnects is presented. The scheme is based on sensing currents on the data wires and comparing the sum of these currents to an appropriately set reference. The goal is to solve the performance bottleneck caused by conventional voltage-mode detection methods. With the channel width of 64 bits, the proposed method is 4.65 times faster and takes 36% less area than the voltage-mode scheme. Furthermore, its speed does not degrade when increasing the channel bit width. It is implemented in a 65 nm CMOS technology.
Ladattava julkaisu This is an electronic reprint of the original article. |  |
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