A4 Vertaisarvioitu artikkeli konferenssijulkaisussa

Multi Network Interface Architectures for Fault Tolerant Network-on-Chip




TekijätRantala V, Lehtonen T, Liljeberg P, Plosila J

Konferenssin vakiintunut nimiInternational Symposium on Signals, Circuits and Systems

Julkaisuvuosi2009

Kokoomateoksen nimi9th International Symposium on Signals, Circuits and Systems, ISSCS 2009

Tietokannassa oleva lehden nimiISSCS 2009: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS,

Sarjan nimi9th International Symposium on Signals, CIrcuits and Systems, ISSCS 2009

Aloitussivu145

Lopetussivu148

Sivujen määrä4

ISBN978-1-4244-3784-9

DOIhttps://doi.org/10.1109/ISSCS.2009.5206183


Tiivistelmä
The topology level fault tolerance of Network-on-Chip (NoC) can be improved with multi network interface (multi-NI) architectures. Multi-NI NoC architectures are based on connecting at least two network interfaces on each core. The aim is to improve fault tolerance on the architectural level which means the delivery of packets even when there are faulty links or routers in the network. This paper presents architectures and algorithms for multi-NI NoCs. The analysis of the proposed architectures and algorithms shows that some of them improve the fault tolerance of NoC with a reasonable overhead by decreasing the average hop counts and keeping the cores connectable even in the case of faults. With a multi-NI architecture the number of successfully delivered packets has been even doubled.



Last updated on 2024-26-11 at 20:52