Jouni Isoaho
Professor
jisoaho@utu.fi +358 40 770 6547 Vesilinnantie 5 Turku ORCID identifier: https://orcid.org/0000-0002-5789-3992 |
Research community or research topic
https://sites.utu.fi/cyber/?lang=en
https://sites.utu.fi/cyber/?lang=en
Publications 
5 of 6
- Fuzzy Logic Based Control for Parallel Cascade Control (2010)
- International Journal on Automatic Control and System Engineering
(A1 Refereed original research article in a scientific journal) - Hierarchical Agent Monitored Parallel On-Chip System: A Novel Design Paradigm and Its Formal Specification (2010)
- International Journal of Embedded and Real-Time Communication Systems
(A1 Refereed original research article in a scientific journal) - Hierarchical Agent Monitoring Design Approach towards Self-Aware Parallel Systems-on-Chip (2010)
- ACM Transactions in Embedded Computing Systems
(A1 Refereed original research article in a scientific journal) - Interconnection alternatives for hierarchical monitoring communication in parallel SoCs (2010)
- Microprocessors and Microsystems
(A1 Refereed original research article in a scientific journal) - ITS Corridor of Cooperative Traffic ICT Project Report (2010)
- TUCS Publication Series
(D4 Published development or research report or study ) - Monitoring and Reconfiguration Techniques for Power Supply Variation Tolerant on-Chip Links (2010)
- IEEE International Symposium on Circuits and Systems. Proceedings
(A4 Refereed article in a conference publication ) - Process Variation Tolerant On-Chip Communication Using Receiver and Driver Reconfiguration (2010) 11th IEEE International Symposium on Quality Electronic Design Nigussie E, Plosila J, Isoaho J
(A4 Refereed article in a conference publication ) - High-speed completion detection for current sensing on-chip interconnects (2009)
- Electronics Letters
(A1 Refereed original research article in a scientific journal) - Analysis of delay variation in encoded on-chip bus signaling under process variation (2008)
- VLSI Design
(A4 Refereed article in a conference publication ) - AREA EFFICIENT DELAY-INSENSITIVE AND DIFFERENTIAL CURRENT SENSING ON-CHIP INTERCONNECT (2008) Proceedings of 2008 IEEE International SOC Conference Nigussie E, Plosila J, Isoaho J
(A4 Refereed article in a conference publication ) - A software defined approach for common baseband processing (2008)
- Journal of Systems Architecture
(A1 Refereed original research article in a scientific journal) - Current mode on-chip interconnect using level-encoded two-phase dual-rail encoding (2007)
- IEEE International Symposium on Circuits and Systems. Proceedings
(A4 Refereed article in a conference publication ) - High-performance long NoC link using delay-insensitive current-mode signaling (2007) Ethiopia Nigussie, Teijo Lehtonen, Sampo Tuuna, Juha Plosila, Jouni Isoaho
(A1 Refereed original research article in a scientific journal) - System Level Simulations (2007) Processor Design. System-On-Chip Computing for ASICs and FPGAs Virtanen S, Truscan D, Määttä S, Westerlund T, Isoaho J, Nurmi J
(A3 Refereed book chapter or chapter in a compilation book) - Analysis of crosstalk and process variations effects on on-chip interconnects (2006) Proceedings of 2006 International Symposium on System-on-Chip Nigussie E, Tuuna S, Plosila J, Isoaho J
(A4 Refereed article in a conference publication ) - An approach for analysing and improving fault tolerance in radio architectures (2006)
- IEEE International Symposium on Circuits and Systems. Proceedings
(A4 Refereed article in a conference publication ) - Delay-insensitive on-chip communication link using low-swing simultaneous bidirectional signaling (2006) Proceedings: IEEE Computer Society Annual Sysmposium on VLSI 2006: Emerging VLSI Technologies and Architectures Nigussie E, Plosila J, Isoaho J
(A4 Refereed article in a conference publication ) - Fault-tolerant routing approach for reconfigurable networks-on-chip (2006)
- International Symposium on System-on-Chip
(A4 Refereed article in a conference publication ) - Full-duplex link implementation using dual-rail encoding and multiple-valued current-mode logic (2006)
- IEEE International Symposium on Circuits and Systems. Proceedings
(A4 Refereed article in a conference publication ) - A Brunch from the Coffee Table-Case Study in NoC Platform Design (2005) Interconnect-Centric Design for Advanced SoC and NoC Ahonen T, Virtanen S, Kylliäinen J, Truscan D, Kasanko T, Sigüenza-Tortosa D, Ristimäki T, Paakkulainen J, Nurmi T, Saastamoinen I, Isännäinen H, Lilius J, Nurmi J, Isoaho J
(A3 Refereed book chapter or chapter in a compilation book)
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