Jouni Isoaho
Professor
jisoaho@utu.fi +358 40 770 6547 Vesilinnantie 5 Turku ORCID identifier: https://orcid.org/0000-0002-5789-3992 |
Research community or research topic
https://sites.utu.fi/cyber/?lang=en
https://sites.utu.fi/cyber/?lang=en
Publications 
5 of 5
- Monitoring and Reconfiguration Techniques for Power Supply Variation Tolerant on-Chip Links (2010)
- IEEE International Symposium on Circuits and Systems. Proceedings
(A4 Refereed article in a conference publication ) - Process Variation Tolerant On-Chip Communication Using Receiver and Driver Reconfiguration (2010) 11th IEEE International Symposium on Quality Electronic Design Nigussie E, Plosila J, Isoaho J
(A4 Refereed article in a conference publication ) - High-speed completion detection for current sensing on-chip interconnects (2009)
- Electronics Letters
(A1 Refereed original research article in a scientific journal) - Analysis of delay variation in encoded on-chip bus signaling under process variation (2008)
- VLSI Design
(A4 Refereed article in a conference publication ) - AREA EFFICIENT DELAY-INSENSITIVE AND DIFFERENTIAL CURRENT SENSING ON-CHIP INTERCONNECT (2008) Proceedings of 2008 IEEE International SOC Conference Nigussie E, Plosila J, Isoaho J
(A4 Refereed article in a conference publication ) - Current mode on-chip interconnect using level-encoded two-phase dual-rail encoding (2007)
- IEEE International Symposium on Circuits and Systems. Proceedings
(A4 Refereed article in a conference publication ) - High-performance long NoC link using delay-insensitive current-mode signaling (2007) Ethiopia Nigussie, Teijo Lehtonen, Sampo Tuuna, Juha Plosila, Jouni Isoaho
(A1 Refereed original research article in a scientific journal) - Analysis of crosstalk and process variations effects on on-chip interconnects (2006) Proceedings of 2006 International Symposium on System-on-Chip Nigussie E, Tuuna S, Plosila J, Isoaho J
(A4 Refereed article in a conference publication ) - Delay-insensitive on-chip communication link using low-swing simultaneous bidirectional signaling (2006) Proceedings: IEEE Computer Society Annual Sysmposium on VLSI 2006: Emerging VLSI Technologies and Architectures Nigussie E, Plosila J, Isoaho J
(A4 Refereed article in a conference publication ) - Full-duplex link implementation using dual-rail encoding and multiple-valued current-mode logic (2006)
- IEEE International Symposium on Circuits and Systems. Proceedings
(A4 Refereed article in a conference publication ) - On asynchronous full-duplex dual-rail link with multiple-valued current-mode signaling (2005) NORCHIP Proceeding Nigussie E, Plosila J, Isoaho J
(A4 Refereed article in a conference publication ) - Reliable asynchronous links for SoC (2005) 2005 International Symposium on System-on-Chip: Proceedings Nigussie E, Plosila J, Isoaho J
(A4 Refereed article in a conference publication ) - Analyses of signaling techniques for self-timed systems (2004) 2004 International Symposium on System-on-Chip Proceedings Ethiopia Nigussie, Johanna Tuominen, Jouni Isoaho
(A4 Refereed article in a conference publication )
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