Boosting Performance of Self-Timed Delay-Insensitive Bit Parallel On-Chip Interconnects - UTU Research Portal

A1 Refereed original research article in a scientific journal

Boosting Performance of Self-Timed Delay-Insensitive Bit Parallel On-Chip Interconnects

Authors: Ethiopia Nigussie, Sampo Tuuna, Juha Plosila, Jouni Isoaho, Hannu Tenhunen

Publisher: The Institution of Engineering and Technology

Publication year: 2011

Journal:IET Circuits, Devices and Systems

Number in series: 6

Volume: 5

Issue: 6

First page : 13

Last page: 517

Number of pages: 505

ISSN: 1751-858X