A4 Refereed article in a conference publication
AREA EFFICIENT DELAY-INSENSITIVE AND DIFFERENTIAL CURRENT SENSING ON-CHIP INTERCONNECT
Authors: Nigussie E, Plosila J, Isoaho J
Conference name: 2008 IEEE International SOC Conference
Publication year: 2008
Book title : Proceedings of 2008 IEEE International SOC Conference
Journal name in source: IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS
Journal acronym: IEEE INT SOC CONF
First page : 143
Last page: 146
Number of pages: 4
ISBN: 978-1-4244-2596-9
ISSN: 2164-1676
DOI: https://doi.org/10.1109/SOCC.2008.4641498
Abstract
We present a noise and delay variations robust high-performance on-chip interconnect based on a new area and power efficient integration of self-timed delay-insensitive data transfer and differential current sensing signaling. Only half number of wires are required compared to conventional integration of the two schemes, making it both area and power efficient. At 5mm wire length a throughput of 1.34Gbps has been achieved and 24% power savings have been gained. The interconnect is designed and simulated using Cadence Spectre with a 65nm CMOS technology.
We present a noise and delay variations robust high-performance on-chip interconnect based on a new area and power efficient integration of self-timed delay-insensitive data transfer and differential current sensing signaling. Only half number of wires are required compared to conventional integration of the two schemes, making it both area and power efficient. At 5mm wire length a throughput of 1.34Gbps has been achieved and 24% power savings have been gained. The interconnect is designed and simulated using Cadence Spectre with a 65nm CMOS technology.
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