Juha Plosila
Head of the Robotics and Autonomous Systems Unit
juplos@utu.fi +358 29 450 2621 +358 50 383 9453 Vesilinnantie 5 Turku ORCID identifier: https://orcid.org/0000-0003-4018-5495 |
autonomous systems; robotics; unmanned vehicles; drones; embedded systems; cyber physical systems; internet of things; smart systems; fog/edge computing; multi-agent systems; multiprocessors; network on chip; system on chip; multiprocessor system on chip; chip multiprocessors; heterogeneous systems; reconfigurable computing; digital circuits and systems; formal methods
Autonomous Systems Laboratory (ASL): https://asl.utu.fi/
Dr. Juha Plosila (born 1965) is Professor (full) in autonomous systems and robotics and the head of the Autonomous Systems Laboratory (ASL) research group (https://asl.utu.fi/) and Smart Systems (formerly Embedded Electronics) cost centre at the University of Turku (UTU) Department of Computing (formerly Department of Future Technologies) since 2019. He received his PhD in electronics and communication technology from UTU in 1999 and his Adjunct Professor (Docent) title in digital systems design in 2006. He held a 5-year position of Academy Research Fellow (Academy of Finland) in 2006-2011 and served as a senior University Lecturer in embedded computing at UTU in 2011-2018. During his tenure at UTU since 2000, he has led many externally funded research projects, supervised more than 20 PhD theses, and served in the management committees of several master's programmes. Plosila has been an active participant in the European Institute of Innovation and Technology (EIT) knowledge and innovation community EIT Digital since 2011, leading the EIT Digital Master Programme in Embedded Systems (a European double-degree programme with 6 partner universities) and representing UTU in the EIT Digital Finland Node Strategy Committee.
Plosila's current research interests include intelligent adaptive and reconfigurable multi-processing platforms, self-aware multi-agent monitoring and control, machine-learning and optimization, as well as application of heterogeneous energy efficient architectures to new computational challenges in the areas of cyber-physical systems and internet-of-things, with a special focus on autonomous multi-robot systems and fog/edge computing. He also has a strong background in network-on-chip design and formal mehods for system design and verification.
Google Scholar statistics: https://scholar.google.com/citations?user=em4kCrUAAAAJ&hl=en
Lecturer for 18 different courses since 1999 in the fields of digital circuit and system design, multiprocessor architectures, computer architectures, reconfigurable computing, embedded systems, modelling and verification, as well as autonomous systems:
Autonomous Systems Architectures, MSc-level, 5 ECTS (2019- ); Regonfigurable Computing, MSc-level, 5 ECTS (at Fudan University, China, 2013- ); Processor Architectures, BSc-level, 5 ECTS (2020); Computer Architectures and Operating Systems, BSc-level, 4 ECTS (2017-2019), Multiprocessor Architectures, MSc-level, 5 ECTS, (2006, -08, -10, 2012-2018); System on Chip Design, MSc-level, 5 ECTS (2015-2016); Seminar on Embedded Computing, MSc/PhD-level, 5 ECTS (2012-2014); Modelling Parallel Systems, MSc-level (2011); Formal System Modelling and Verification, MSc-level, 5 ECTS, (2008, -10); Post Graduate Course on Digital Circuit & System Design, PhD-level; 5 ECTS (2009); Advanced Multiprocessor Systems, MSc-level, 5 ECTS (2009); System Verification, MSc-level, 5 ECTS (2007); Computer Architectures, BSc-level, 7 ECTS (2006-2007); Asynchronous System Design, MSc-level, 5 ECTS (2003, -05, -07); Formal System Specification and Design, MSc-level; 10 ECTS (2004, -06); Digital Integrated Circuit Design, BSc-level, 7 ECTS (2000-2005); Digital Systems Engineering, MSc-level, 10 ECTS (2001, -02, -04); Principles of Digital Design, BSc-level, 5 ECTS (1999-2000, -04).
- Compact Generic Intermediate representation to enable late binding in Coarse Grained Reconfigurable Architectures (2011) Proc. International Conference on Field-Programmable Technology (FPT), 2011 Syed Mohammad Asad Hassan Jafri, Kolin Paul, Ahmed Hemani, Juha Plosila, Hannu Tenhunen
(A4 Refereed article in a conference publication ) - Compression Based Efficient and agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures (2011) International Parallel and Distributed Processing Symposium 2011 Syed Mohammad Asad Hassan Jafri, Kolin Paul, Ahmed Hemani, Juha Plosila, Hannu Tenhunen
(A4 Refereed article in a conference publication ) - Congestion Aware, Fault Tolerant, and Thermally Efficient Inter-Layer Communication Scheme for Hybrid NoC-Bus 3D Architectures (2011) IEEE/ACM Rahmani Amir-Mohammad, Latif Khalid, Vaddina Kameswar Rao, Liljeberg Pasi, Plosila Juha, Tenhunen Hannu
(A4 Refereed article in a conference publication ) - Efficient congestion-aware selection method for on-chip networks (2011) Daneshtalab Masoud, Ebrahimi Masoumeh, Liljeberg Pasi, Plosila Juha, Tenhunen Hannu
(A4 Refereed article in a conference publication ) - Exploration of MPSoC monitoring and management systems (2011) Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2011 6th International Workshop on Fattah M, Daneshtalab M, Liljeberg P, Plosila J
(A4 Refereed article in a conference publication ) - Exploring Cluster-Based Topologies for 3D Stacked Architectures (2011) Daneshtalab Masoud, Ebrahimi Masoumeh, Liljeberg Pasi, Plosila Juha, Tenhunen Hannu
(A4 Refereed article in a conference publication ) - Exploring Partitioning Methods for 3D Networks-on-Chip Utilizing Adaptive Routing Model (2011) Ebrahimi Masoumeh, Daneshtalab Masoud, Liljeberg Pasi, Plosila Juha, Tenhunen Hannu
(A4 Refereed article in a conference publication ) - HAMSoC: A Monitoring-Centric Design Approach for Adaptive Parallel Computing (2011) Autonomic Networking-on-Chip: Bio-inspired Specification, Development and Verification Guang Liang, Plosila Juha, Isoaho Jouni, Tenhunen Hannu
(A3 Refereed book chapter or chapter in a compilation book) - Hierarchical Agent Monitoring Design Platform towards Self-aware and Adaptive Embedded Systems (2011) Guang Liang, Yang Bo, Plosila Juha, Isoaho Jouni, Tenhunen Hannu
(A4 Refereed article in a conference publication ) - Hierarchical Monitoring in Smart House: Design Scalability, Dependability and Energy-Efficiency (2011) Proc. of the 3rd International Conference on Information Science and Engineering (ICISE2011) Guang L, Kanth R, Plosila J, Tenhunen H
(A4 Refereed article in a conference publication ) - High-Performance On-Chip Network Platform for Memory-on-Processor Architectures (2011) Daneshtalab Masoud, Ebrahimi Masoumeh, Liljeberg Pasi, Plosila Juha, Tenhunen Hannu
(A4 Refereed article in a conference publication ) - LastZ: An Ultra Optimized 3D Networks-on-Chip Architecture (2011)
- Digital System Design
(A4 Refereed article in a conference publication ) - Power-Aware Architecture for 3D Networks-on-Chip (2011) Euromicro Rahmani Amir-Mohammad, Latif Khalid, Liljeberg Pasi, Plosila Juha, Tenhunen Hannu
(A4 Refereed article in a conference publication ) - Power-Efficient Inter-Layer Communication Architectures for 3D NoC (2011)
- IEEE Computer Society Annual Symposium on VLSI
(A4 Refereed article in a conference publication ) - Q-learning based congestion-aware routing algorithm for on-chip network. (2011) Fahimeh Farahnakian, Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila
(A4 Refereed article in a conference publication ) - Thermal Analysis of Advanced 3D Stacked Systems (2011)
- IEEE Computer Society Annual Symposium on VLSI
(A4 Refereed article in a conference publication ) - Thermal Analysis of Job Allocation and Scheduling Schemes for 3D Stacked NoC's (2011)
- Digital System Design
(A4 Refereed article in a conference publication ) - Thermal Modeling and Analysis of Advanced 3D Stacked Structures (2011) Elsevier Kameswar Rao Vaddina, Rahmani Amir-Mohammad, Latif Khalid, Liljeberg Pasi, Plosila Juha
(A4 Refereed article in a conference publication ) - Towards Self-Placing Applications on a 3D-NoC (2011) Autonomic Networking-on-Chip: Bio-inspired Specification, Development and Verification Luigia Petre, Kaisa Sere, Leonidas Tsiopoulos, Pasi Liljeberg, Juha Plosila
(A3 Refereed book chapter or chapter in a compilation book) - Tree-Model Based Contention-Aware Task Mapping on Many-Core Network-on-Chips. (2011) IEEE Yang Bo, Guang Liang, Säntti Tero, Plosila Juha
(A4 Refereed article in a conference publication )
