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Architectural modeling of pixel readout chips Velopix and Timepix3




TekijätPoikela T, Plosila J, Westerlund T, Buytaert J, Campbell M, Llopart X, Plackett R, Wyllie K, Beuzekom M, Gromov V, Kluit R, Zappon F, Zivkovic V, Brezina C, Desch K, Fang X, Kruth A

Julkaisuvuosi2012

JournalJournal of Instrumentation

Tietokannassa oleva lehden nimiJournal of Instrumentation

Numero sarjassa01

Vuosikerta7

Numero01

Aloitussivu1

Lopetussivu7

Sivujen määrä8

ISSN1748-0221

DOIhttps://doi.org/10.1088/1748-0221/7/01/C01093

Verkko-osoitehttp://stacks.iop.org/1748-0221/7/i=01/a=C01093


Tiivistelmä
We examine two digital architectures for front end pixel readout chips, Velopix and Timepix3. These readout chips are developed for tracking detectors in future high energy physics experiments. They must incorporate local intelligence in pixels for time-over-threshold measurement and sparse readout. In addition, Velopix must be immune to single-event upsets in its digital logic. The most important requirements for both chips are pixel size, timing resolution, low power and high-speed sparse readout. We describe the transaction level architectural models of the chips using SystemVerilog. The correctness of the models is ensured using Open Verification Methodology. We will also discuss the advantages gained from transaction level modeling.



Last updated on 2024-26-11 at 21:37