A1 Refereed original research article in a scientific journal
Architectural modeling of pixel readout chips Velopix and Timepix3
Authors: Poikela T, Plosila J, Westerlund T, Buytaert J, Campbell M, Llopart X, Plackett R, Wyllie K, Beuzekom M, Gromov V, Kluit R, Zappon F, Zivkovic V, Brezina C, Desch K, Fang X, Kruth A
Publication year: 2012
Journal: Journal of Instrumentation
Journal name in source: Journal of Instrumentation
Number in series: 01
Volume: 7
Issue: 01
First page : 1
Last page: 7
Number of pages: 8
ISSN: 1748-0221
DOI: https://doi.org/10.1088/1748-0221/7/01/C01093
Web address : http://stacks.iop.org/1748-0221/7/i=01/a=C01093
Abstract
We examine two digital architectures for front end pixel readout chips, Velopix and Timepix3. These readout chips are developed for tracking detectors in future high energy physics experiments. They must incorporate local intelligence in pixels for time-over-threshold measurement and sparse readout. In addition, Velopix must be immune to single-event upsets in its digital logic. The most important requirements for both chips are pixel size, timing resolution, low power and high-speed sparse readout. We describe the transaction level architectural models of the chips using SystemVerilog. The correctness of the models is ensured using Open Verification Methodology. We will also discuss the advantages gained from transaction level modeling.
We examine two digital architectures for front end pixel readout chips, Velopix and Timepix3. These readout chips are developed for tracking detectors in future high energy physics experiments. They must incorporate local intelligence in pixels for time-over-threshold measurement and sparse readout. In addition, Velopix must be immune to single-event upsets in its digital logic. The most important requirements for both chips are pixel size, timing resolution, low power and high-speed sparse readout. We describe the transaction level architectural models of the chips using SystemVerilog. The correctness of the models is ensured using Open Verification Methodology. We will also discuss the advantages gained from transaction level modeling.
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