A4 Refereed article in a conference publication
Fault-tolerant routing approach for reconfigurable networks-on-chip
Authors: Rantala P, Lehtonen T, Isoaho J, Plosila J
Publication year: 2006
Journal:: International Symposium on System-on-Chip
Book title : International Symposium on System-on-Chip 2006
Journal name in source: 2006 International Symposium on System-on-Chip Proceedings
First page : 107
Last page: 110
Number of pages: 4
ISBN: 978-1-4244-0621-0
Abstract
We introduce fault-tolerant on-chip routing philosophy for two-dimensional meshes. It is an extension to the concept of packet connected circuit, PCC. In order to increase reliability we have designed an automatic rerouting property to a single switch node and added return channel to the communication route. An autonomic routing switch node is modeled asynchronously and implemented using Haste language. The logical functionality of routing is illustrated as a single study case in 7*8 mesh. The routing success is further analyzed in congesting and faulty environment.
We introduce fault-tolerant on-chip routing philosophy for two-dimensional meshes. It is an extension to the concept of packet connected circuit, PCC. In order to increase reliability we have designed an automatic rerouting property to a single switch node and added return channel to the communication route. An autonomic routing switch node is modeled asynchronously and implemented using Haste language. The logical functionality of routing is illustrated as a single study case in 7*8 mesh. The routing success is further analyzed in congesting and faulty environment.
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