A4 Vertaisarvioitu artikkeli konferenssijulkaisussa
Fault-tolerant routing approach for reconfigurable networks-on-chip
Tekijät: Rantala P, Lehtonen T, Isoaho J, Plosila J
Julkaisuvuosi: 2006
Lehti:: International Symposium on System-on-Chip
Kokoomateoksen nimi: International Symposium on System-on-Chip 2006
Tietokannassa oleva lehden nimi: 2006 International Symposium on System-on-Chip Proceedings
Aloitussivu: 107
Lopetussivu: 110
Sivujen määrä: 4
ISBN: 978-1-4244-0621-0
Tiivistelmä
We introduce fault-tolerant on-chip routing philosophy for two-dimensional meshes. It is an extension to the concept of packet connected circuit, PCC. In order to increase reliability we have designed an automatic rerouting property to a single switch node and added return channel to the communication route. An autonomic routing switch node is modeled asynchronously and implemented using Haste language. The logical functionality of routing is illustrated as a single study case in 7*8 mesh. The routing success is further analyzed in congesting and faulty environment.
We introduce fault-tolerant on-chip routing philosophy for two-dimensional meshes. It is an extension to the concept of packet connected circuit, PCC. In order to increase reliability we have designed an automatic rerouting property to a single switch node and added return channel to the communication route. An autonomic routing switch node is modeled asynchronously and implemented using Haste language. The logical functionality of routing is illustrated as a single study case in 7*8 mesh. The routing success is further analyzed in congesting and faulty environment.
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