Juha Plosila
Head of the Robotics and Autonomous Systems Unit
juplos@utu.fi +358 29 450 2621 +358 50 383 9453 Vesilinnantie 5 Turku ORCID identifier: https://orcid.org/0000-0003-4018-5495 |
autonomous systems; robotics; unmanned vehicles; drones; embedded systems; cyber physical systems; internet of things; smart systems; fog/edge computing; multi-agent systems; multiprocessors; network on chip; system on chip; multiprocessor system on chip; chip multiprocessors; heterogeneous systems; reconfigurable computing; digital circuits and systems; formal methods
Autonomous Systems Laboratory (ASL): https://asl.utu.fi/
Dr. Juha Plosila (born 1965) is Professor (full) in autonomous systems and robotics and the head of the Autonomous Systems Laboratory (ASL) research group (https://asl.utu.fi/) and Smart Systems (formerly Embedded Electronics) cost centre at the University of Turku (UTU) Department of Computing (formerly Department of Future Technologies) since 2019. He received his PhD in electronics and communication technology from UTU in 1999 and his Adjunct Professor (Docent) title in digital systems design in 2006. He held a 5-year position of Academy Research Fellow (Academy of Finland) in 2006-2011 and served as a senior University Lecturer in embedded computing at UTU in 2011-2018. During his tenure at UTU since 2000, he has led many externally funded research projects, supervised more than 20 PhD theses, and served in the management committees of several master's programmes. Plosila has been an active participant in the European Institute of Innovation and Technology (EIT) knowledge and innovation community EIT Digital since 2011, leading the EIT Digital Master Programme in Embedded Systems (a European double-degree programme with 6 partner universities) and representing UTU in the EIT Digital Finland Node Strategy Committee.
Plosila's current research interests include intelligent adaptive and reconfigurable multi-processing platforms, self-aware multi-agent monitoring and control, machine-learning and optimization, as well as application of heterogeneous energy efficient architectures to new computational challenges in the areas of cyber-physical systems and internet-of-things, with a special focus on autonomous multi-robot systems and fog/edge computing. He also has a strong background in network-on-chip design and formal mehods for system design and verification.
Google Scholar statistics: https://scholar.google.com/citations?user=em4kCrUAAAAJ&hl=en
Lecturer for 18 different courses since 1999 in the fields of digital circuit and system design, multiprocessor architectures, computer architectures, reconfigurable computing, embedded systems, modelling and verification, as well as autonomous systems:
Autonomous Systems Architectures, MSc-level, 5 ECTS (2019- ); Regonfigurable Computing, MSc-level, 5 ECTS (at Fudan University, China, 2013- ); Processor Architectures, BSc-level, 5 ECTS (2020); Computer Architectures and Operating Systems, BSc-level, 4 ECTS (2017-2019), Multiprocessor Architectures, MSc-level, 5 ECTS, (2006, -08, -10, 2012-2018); System on Chip Design, MSc-level, 5 ECTS (2015-2016); Seminar on Embedded Computing, MSc/PhD-level, 5 ECTS (2012-2014); Modelling Parallel Systems, MSc-level (2011); Formal System Modelling and Verification, MSc-level, 5 ECTS, (2008, -10); Post Graduate Course on Digital Circuit & System Design, PhD-level; 5 ECTS (2009); Advanced Multiprocessor Systems, MSc-level, 5 ECTS (2009); System Verification, MSc-level, 5 ECTS (2007); Computer Architectures, BSc-level, 7 ECTS (2006-2007); Asynchronous System Design, MSc-level, 5 ECTS (2003, -05, -07); Formal System Specification and Design, MSc-level; 10 ECTS (2004, -06); Digital Integrated Circuit Design, BSc-level, 7 ECTS (2000-2005); Digital Systems Engineering, MSc-level, 10 ECTS (2001, -02, -04); Principles of Digital Design, BSc-level, 5 ECTS (1999-2000, -04).
- A Dynamic Fault-Tolerant Remapping Algorithm Based on Tree-Model of Network-on-Chip (2010)
- Proceedings : Design, Automation, and Test in Europe Conference and Exhibition
(A4 Refereed article in a conference publication ) - A Fault-Tolerant and Congestion-Aware Routing Algorithm for Networks-on-Chip (2010) Proc. of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Valinataj M, Mohammadi S, Plosila J, Liljeberg P
(A4 Refereed article in a conference publication ) - A High-Performance Network Interface Architecture for NoCs Using Reorder Buffer Sharing (2010)
- Proceedings: Euromicro Workshop on Parallel and Distributed Processing
(A4 Refereed article in a conference publication ) - A Low-Latency and Memory-Efficient On-Chip Network (2010) The 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS) Daneshtalab M, Ebrahimi M, Liljeberg P, Plosila J, Tenhunen H
(A4 Refereed article in a conference publication ) - An Efficient VFI-Based NoC Architecture Using Johnson-Encoded Reconfigurable FIFOs (2010) Proc. of IEEE International Norchip Conference (NORCHIP 10) Rahmani A-M, Liljeberg P, Plosila J, Tenhunen H
(A4 Refereed article in a conference publication ) - An Improved Hardware Acceleration Scheme for Java Method Calls (2010) Norchip 2010 Säntti T, Tyystjärvi J, Plosila J
(A4 Refereed article in a conference publication ) - BBVC-3D-NoC: An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels (2010)
- IEEE Computer Society Annual Symposium on VLSI
(A4 Refereed article in a conference publication ) - CMIT- A Novel Cluster-Based Topology for 3D Stacked Architectures (2010) IEEE International 3D Systems Integration Conference (3DIC) Daneshtalab M, Ebrahimi M, Liljeberg P, Plosila J, Tenhunen H
(A4 Refereed article in a conference publication ) - Current Challenges in Embedded Communication Systems (2010)
- International Journal of Embedded and Real-Time Communication Systems
(A1 Refereed original research article in a scientific journal) - Developing Reconfigurable FIFOs to Optimize Power/Performance of Voltage/Frequency Island-Based Networks-on-Chip (2010) IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems Rahmani A-M, Liljeberg P, Plosila J, Tenhunen H
(A4 Refereed article in a conference publication ) - Efficient Bytecode Optimizations for a Multicore Java Co-Processor System (2010) 2010 12th Biennial Baltic Electronics Conference (BEC2010) Tyystjärvi J, Säntti T, Plosila J
(A4 Refereed article in a conference publication ) - Exploring a Low-Cost Inter-layer Communication Scheme for 3D Networks-on-Chip (2010) Proc. of IEEE 15th International Symposium on Computer Architecture & Digital Systems (CADS’10) Rahmani A-M, Liljeberg P, Plosila J, Tenhunen H
(A4 Refereed article in a conference publication ) - Heap Access Optimizations for a Hardware-Accelerated Java Virtual Machine (2010) 2010 International Symposium on System-on-Chip Tyystjärvi J, Säntti T, Plosila J
(A4 Refereed article in a conference publication ) - Hierarchical Agent Monitored Parallel On-Chip System: A Novel Design Paradigm and Its Formal Specification (2010)
- International Journal of Embedded and Real-Time Communication Systems
(A1 Refereed original research article in a scientific journal) - Hierarchical Power Monitoring on NoC- A Case Study for Hierarchical Agent Monitoring Design Approach (2010) Proceedings of IEEE Norchip 2010 Guang L, Yang B, Plosila J, Latif K, Tenhunen H
(A4 Refereed article in a conference publication ) - High-Performance TSV Architecture for 3-D ICs (2010)
- IEEE Computer Society Annual Symposium on VLSI
(A4 Refereed article in a conference publication ) - Input-Output Selection Based Router for Networks-on-Chip (2010)
- IEEE Computer Society Annual Symposium on VLSI
(A4 Refereed article in a conference publication ) - Modelling Communication in Multi-Processor Systems-on-Chip Using Modular Connectors (2010)
- International Journal of Embedded and Real-Time Communication Systems
(A1 Refereed original research article in a scientific journal) - Monitoring and Reconfiguration Techniques for Power Supply Variation Tolerant on-Chip Links (2010)
- IEEE International Symposium on Circuits and Systems. Proceedings
(A4 Refereed article in a conference publication ) - Multi-Application Mapping Algorithm for Network-on-Chip Platforms (2010) Proc. of the 26th IEEE Convention of Electrical and Electronics Engineers in Israel (IEEEI) Yang B, Guang L, Xu T C, Säntti T, Plosila J
(A4 Refereed article in a conference publication )
