A1 Refereed original research article in a scientific journal
Performance and programmability comparison of the thick control flow architecture and current multicore processors
Authors: Forsell Martti, Nikula Sara, Roivainen Jussi, Leppänen Ville, Träff Jesper Larsson
Publisher: Springer
Publication year: 2022
Journal: Journal of Supercomputing
Journal name in source: JOURNAL OF SUPERCOMPUTING
Journal acronym: J SUPERCOMPUT
Volume: 78
First page : 3152
Last page: 3183
Number of pages: 32
ISSN: 0920-8542
eISSN: 1573-0484
DOI: https://doi.org/10.1007/s11227-021-03985-0
Web address : https://link.springer.com/article/10.1007/s11227-021-03985-0
Self-archived copy’s web address: https://research.utu.fi/converis/portal/detail/Publication/66529371
Commercial multicore central processing units (CPU) integrate a number of processor cores on a single chip to support parallel execution of computational tasks. Multicore CPUs can possibly improve performance over single cores for independent parallel tasks nearly linearly as long as sufficient bandwidth is available. Ideal speedup is, however, difficult to achieve when dense intercommunication between the cores or complex memory access patterns is required. This is caused by expensive synchronization and thread switching, and insufficient latency toleration. These facts guide programmers away from straight-forward parallel processing patterns toward complex and error-prone programming techniques. To address these problems, we have introduced the Thick control flow (TCF) Processor Architecture. TCF is an abstraction of parallel computation that combines self-similar threads into computational entities. In this paper, we compare the performance and programmability of an entry-level TCF processor and two Intel Skylake multicore CPUs on commonly used parallel kernels to find out how well our architecture solves these issues that greatly reduce the productivity of parallel software development. Code examples are given and programming experiences recorded.
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