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ECDR2: Error Corrector and Detector Relocation Router for Network-on-Chip
Tekijät: Huang Letian, Yuan Chikun, Wang Junshi, Ebrahimi Masoumeh, Xie Xuan, Li Quan
Kustantaja: IEEE COMPUTER SOC
Julkaisuvuosi: 2021
Journal: IEEE Transactions on Computers
Tietokannassa oleva lehden nimi: IEEE TRANSACTIONS ON COMPUTERS
Lehden akronyymi: IEEE T COMPUT
Vuosikerta: 70
Numero: 4
Aloitussivu: 606
Lopetussivu: 613
Sivujen määrä: 8
ISSN: 0018-9340
eISSN: 1557-9956
DOI: https://doi.org/10.1109/TC.2020.2991749
Verkko-osoite: https://ieeexplore.ieee.org/document/9086887
Tiivistelmä
Network-on-chip (NoC) is commonly used in modern many-core systems due to their high bandwidth and flexibility. As the manufacturing process keeps scaling, the reliability challenge in NoCs increases as well. The error correction code (ECC) is widely adopted in error correction NoCs to improve the data correctness. At the same time, extra stages are introduced in the router pipeline to improve the error correction capability. As a result, conventional error correction routers suffer from high network latency. Motivated by this limitation, i.e., we remove the extra pipeline stages delicately introduced for error correction. We propose an error correction router, called error corrector and detector relocation router (ECDR2), whose architecture optimizes the pipeline flow of the router. As a result, it can achieve both low latency and high error correction.Experimental results show that, compared with the baseline design, ECDR2 obtains 13.67 and 39.4 percent less average latency under the uniform traffic pattern and Dedup benchmark, respectively, in an 8 x 8 mesh NoC. The circuit area of ECR is also 7.9 percent less than that of the baseline design under 45-nm technology.
Network-on-chip (NoC) is commonly used in modern many-core systems due to their high bandwidth and flexibility. As the manufacturing process keeps scaling, the reliability challenge in NoCs increases as well. The error correction code (ECC) is widely adopted in error correction NoCs to improve the data correctness. At the same time, extra stages are introduced in the router pipeline to improve the error correction capability. As a result, conventional error correction routers suffer from high network latency. Motivated by this limitation, i.e., we remove the extra pipeline stages delicately introduced for error correction. We propose an error correction router, called error corrector and detector relocation router (ECDR2), whose architecture optimizes the pipeline flow of the router. As a result, it can achieve both low latency and high error correction.Experimental results show that, compared with the baseline design, ECDR2 obtains 13.67 and 39.4 percent less average latency under the uniform traffic pattern and Dedup benchmark, respectively, in an 8 x 8 mesh NoC. The circuit area of ECR is also 7.9 percent less than that of the baseline design under 45-nm technology.
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