A4 Refereed article in a conference publication
Electrical Modeling of Randomly Oriented Copper Nanowire Networks
Authors: Matić, M.; Sharma, V.; Poljak, M.
Editors: Babic, Snjezana; Car, Zeljka; Cicin-Sain, Marina; Ergovic, Pavle; Galinac Grbac, Tihana; Gros, Stjepan; Jovic, Alan; Jurekovic, Darko; Katulic, Tihomir; Koricic, Marko; Kralj, Nenad; Mornar, Vedran; Petrovic, Juraj; Skala, Karolj; Skvorc, Dejan; Sruk, Vlado; Tijan, Edvard; Valacich, Joe; Vrcek, Neven; Vrdoljak, Boris
Conference name: MIPRO ICT and Electronics Convention
Publication year: 2026
Journal: International Convention on Information and Communication Technology, Electronics and Microelectronics
Book title : 2026 49th MIPRO ICT and Electronics Convention (MIPRO)
Volume: 49
First page : 1712
Last page: 1717
ISBN: 979-8-3315-6310-3
eISBN: 979-8-3315-6309-7
ISSN: 1847-3938
eISSN: 1847-3946
DOI: https://doi.org/10.1109/MIPRO70003.2026.11591663
Publication's open availability at the time of reporting: No Open Access
Publication channel's open availability : No Open Access publication channel
Web address : https://ieeexplore.ieee.org/document/11591663
Copper nanowire (CuNW) networks are promising candidates for flexible, transparent conductive surfaces and nanoelectronic interconnects due to their high intrinsic conductivity and compatibility with scalable fabrication methods. The electrical performance of CuNW networks is strongly influenced by network topology, nanowire geometry, and inter-nanowire junction properties. In this work, we present an efficient and scalable modeling framework for large CuNW networks with arbitrary patterns and apply it to study the sheet resistance of randomly oriented CuNW networks. Individual nanowires are described using physically accurate resistivity models that account for surface and grain-boundary effects, while inter-nanowire interactions are represented by resistive junctions. This approach is used to investigate computational limitations and the impact of leakage on sheet resistance in randomly oriented CuNW networks. The results show that up to an 8.6× speedup can be achieved by parallelization on 20 cores, but this comes at the cost of high RAM usage, up to 120 GB , which limits parallelization. Furthermore, due to leakage, sheet resistance is up to 1.7× higher than without leakage for structures with low mass density and low contact quality, while for higher mass density, its impact is lower, at the sub- 1.2× level.
Funding information in the publication:
This work was done as part of the project DURATRANS supported by M-ERA.NET 3, which is co-funded by the European Union Horizon 2020 research and innovation programme under grant agreement No. 958174. M.P. acknowledges support by the Ministry of Science, Education and Youth of the Republic of Croatia.
