Deep Learning and Generative AI for Monolithic and Chiplet SoC Design and Verification: A Survey
: Ben Dhaou, Imed; Larguech, Syhem; Rajendran, Sree Ranjani; Chakraborty, Rajat Subhra; Tenhunen, Hannu; Abdelgawad, Ahmed
Publisher: Now Publishers
: 2025
Foundations and Trends in Electronic Design Automation
Foundations and Trends® in Electronic Design Automation
: 14
: 4
: 245
: 294
: 1551-3939
: 1551-3947
DOI: https://doi.org/10.1561/1000000063-1
: https://www.nowpublishers.com/article/Details/EDA-063-1
The rapid development of integrated circuit (IC) technology, driven by the growing demand for Internet of Things (IoT) devices, cloud computing, and cyber-physical systems, has introduced significant challenges in the design and verification of modern System-on-Chip (SoC) systems. Contemporary SoCs, whether used in desktops or servers, are extremely complex with billions of transistors and often use mixed-core technologies. Designing complex SoCs in modern technologies faces issues in scalability, security, verification, and design optimization, especially as the industry transitions to chipset-based architectures. In this work, we explore the potential of deep learning and generative Artificial Intelligence (AI) to address these challenges, focusing on applications in Register Transfer Level (RTL) code generation, design automation, hardware security, and verification.
In this work, we review the state-of-the-art in AI-driven Electronic Design Automation (EDA) tools, examining both open source and commercial platforms that have integrated AI to enhance design efficiency and performance. The work focuses on AI’s role in optimizing power, performance, and area (PPA) metrics, as well as improving hardware security by mitigating threats such as hardware Trojans. In addition, we discuss the implications of adopting AI in SoC workflows and its transformative potential in democratizing hardware design.