A4 Refereed article in a conference publication
A 512×512-cell associative CAM/Willshaw memory with vector arithmetic
Authors: Mika Laiho, Jonne Poikonen, Eero Lehtonen, Mikko Pänkäälä, Jussi Poikonen, Pentti Kanerva
Conference name: IEEE International Symposium on Circuits and Systems
Publication year: 2015
Book title : Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Series title: ISCAS
First page : 1350
Last page: 1353
ISBN: 978-1-4799-8391-9
ISSN: 0271-4302
DOI: https://doi.org/10.1109/ISCAS.2015.7168892
Web address : http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7168892
In this paper we present a CMOS implementation of a 512×512-cell Associative Content Addressable Memory (ACAM) in 180 nm CMOS. The memory can be operated either as an associative CAM or it can be configured into a Willshaw memory for operating with sparse data. The vector matching operation can use a tunable hit threshold or the strongest hit can be selected with a winner-take-all (WTA) network. Built-in row and column circuitry can perform logic operations on the contents of the row and column memories. The operation of the circuit is verified experimentally with an example on computing with random vectors.
