A4 Vertaisarvioitu artikkeli konferenssijulkaisussa
Fault tolerance analysis of NoC architectures
Tekijät: Lehtonen T, Liljeberg P, Plosila J
Julkaisuvuosi: 2007
Lehti:IEEE International Symposium on Circuits and Systems. Proceedings
Kokoomateoksen nimi: IEEE International Symposium on Circuits and Systems, ISCAS 2007
Tietokannassa oleva lehden nimi2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11
Lehden akronyymi: IEEE INT SYMP CIRC S
Aloitussivu: 361
Lopetussivu: 364
Sivujen määrä: 4
ISBN: 978-1-4244-0920-4
ISSN: 0271-4302
DOI: https://doi.org/10.1109/ISCAS.2007.378464
Tiivistelmä
We present an approach for analyzing and improving fault tolerance aspects in NoC architectures. This is a necessary step to be taken in order to implement reliable systems in future nanoscale technologies. Several NoC architectures and the router structures as well as the network interface needed for them are presented and compared for their fault tolerance, area and performance. The results indicate that a network structure built from simple 3-port routers provides better fault tolerance than a structure based on more complex multiport routers, and that the area overhead can be kept moderate.
We present an approach for analyzing and improving fault tolerance aspects in NoC architectures. This is a necessary step to be taken in order to implement reliable systems in future nanoscale technologies. Several NoC architectures and the router structures as well as the network interface needed for them are presented and compared for their fault tolerance, area and performance. The results indicate that a network structure built from simple 3-port routers provides better fault tolerance than a structure based on more complex multiport routers, and that the area overhead can be kept moderate.
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