A4 Refereed article in a conference publication
Fault tolerance analysis of NoC architectures
Authors: Lehtonen T, Liljeberg P, Plosila J
Publication year: 2007
Journal:IEEE International Symposium on Circuits and Systems. Proceedings
Book title : IEEE International Symposium on Circuits and Systems, ISCAS 2007
Journal name in source2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11
Journal acronym: IEEE INT SYMP CIRC S
First page : 361
Last page: 364
Number of pages: 4
ISBN: 978-1-4244-0920-4
ISSN: 0271-4302
DOI: https://doi.org/10.1109/ISCAS.2007.378464
Abstract
We present an approach for analyzing and improving fault tolerance aspects in NoC architectures. This is a necessary step to be taken in order to implement reliable systems in future nanoscale technologies. Several NoC architectures and the router structures as well as the network interface needed for them are presented and compared for their fault tolerance, area and performance. The results indicate that a network structure built from simple 3-port routers provides better fault tolerance than a structure based on more complex multiport routers, and that the area overhead can be kept moderate.
We present an approach for analyzing and improving fault tolerance aspects in NoC architectures. This is a necessary step to be taken in order to implement reliable systems in future nanoscale technologies. Several NoC architectures and the router structures as well as the network interface needed for them are presented and compared for their fault tolerance, area and performance. The results indicate that a network structure built from simple 3-port routers provides better fault tolerance than a structure based on more complex multiport routers, and that the area overhead can be kept moderate.
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