A4 Refereed article in a conference publication
Supporting Concurrent Memory Access in TCF-aware Processor Architectures
Authors: Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Träff
Editors: Jari Nurmi, Mark Vesterbacka, J. Jacob Wikner, Atila Alvandpour, Martin Nielsen-Lönn, Ivan Ring Nielsen
Conference name: Nordic Circuits and Systems Conference
Publication year: 2017
Book title : Proceedings of Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)
First page : 1
Last page: 6
Number of pages: 6
ISBN: 978-1-5386-2845-4
eISBN: 978-1-5386-2844-7
DOI: https://doi.org/10.1109/NORCHIP.2017.8124962
Web address : http://ieeexplore.ieee.org/document/8124962/
Self-archived copy’s web address: https://research.utu.fi/converis/portal/detail/Publication/290065560
The Thick Control Flow (TCF) model packs together selfsimilar
computations to simplify parallel programming and to eliminate
redundant usage of associated software and hardware resources.
While there are processor architectures supporting native execution
of programs written for the model, none of them support concurrent
memory access that can speed up execution of many algorithms by a
logarithmic factor. In this paper, we propose an architectural solution
implementing concurrent memory access for TCF-aware processors.
The solution is based on bounded size step caches and two-phase
structure of the TCF-aware processors. Step caches capture and hold
the references made during the on-going step of an execution that
are independent by the definition of TCF execution and therefore
avoid coherence problems. The 2-phase structure reduces some concurrent
accesses to a frontend operation followed by broadcast in the
spreading network. According to our evaluation, a concurrent memory
access-aware B-backend unit TCF processor executes certain algorithms
up to B times faster than the baseline TCF processor.
Downloadable publication This is an electronic reprint of the original article. |  |
