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A cellular computing architecture for parallel memristive stateful logic
Tekijät: Eero Lehtonen, Jari Tissari, Jussi Poikonen, Mika Laiho, Lauri Koskinen
Kustantaja: Elsevier
Julkaisuvuosi: 2014
Journal: Microelectronics Journal
Vuosikerta: 45
Numero: 11
Aloitussivu: 1438
Lopetussivu: 1449
Sivujen määrä: 12
ISSN: 0026-2692
DOI: https://doi.org/10.1016/j.mejo.2014.09.005
Verkko-osoite: http://www.sciencedirect.com/
Tiivistelmä
We present a cellular memristive stateful logic computing architecture and demonstrate its operation with computational examples such as vectorized XOR, circular shift, and content-addressable memory. The considered architecture can perform parallel elementary memristor programming and stateful logic operations, namely implication and converse nonimplication. The topology of the crossbar structure used for computing can be dynamically reconfigured, enabling combinations of local and global operations with varying granularity. In the CMOS cells used for controlling the memristors, we apply a new type of capacitive keeper circuit, which allows for energy efficient implementation of logic operations. The correct operation of this architecture is verified by detailed HSPICE simulations for a structure containing eight memristive crossbars. This work presents a hardware platform which enables future work on parallel stateful computing.
We present a cellular memristive stateful logic computing architecture and demonstrate its operation with computational examples such as vectorized XOR, circular shift, and content-addressable memory. The considered architecture can perform parallel elementary memristor programming and stateful logic operations, namely implication and converse nonimplication. The topology of the crossbar structure used for computing can be dynamically reconfigured, enabling combinations of local and global operations with varying granularity. In the CMOS cells used for controlling the memristors, we apply a new type of capacitive keeper circuit, which allows for energy efficient implementation of logic operations. The correct operation of this architecture is verified by detailed HSPICE simulations for a structure containing eight memristive crossbars. This work presents a hardware platform which enables future work on parallel stateful computing.
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