PEN: A Power-law Enhanced Network Design for High Efficiency Multicore Architecture

: Thomas Xu, Ville Leppänen

Publisher: John Wiley & Sons Ltd.

: 2017

: Concurrency and Computation: Practice and Experience

: 29

: 16

: 9

: 1532-0626

: 1532-0634

DOI: https://doi.org/10.1002/cpe.3988

: http://onlinelibrary.wiley.com/doi/10.1002/cpe.3988/epdf

We propose a heterogeneous on-chip interconnection aiming at high efficiency multicore pro-cessors. An ideal on-chip interconnection should have low latency, high throughput, low powerconsumption, and high scalability. However, these metrics are usually contradictory with eachother. Besides, a design should focus on the requirements of real applications. We investigate thecharacteristics of several parallel applications. It is found that the distribution of traffic is similaras the power law. We also discovered hot spot traffic, as well as bursty traffic from applications.Meanwhile, the average injection rate of parallel applications is relatively low. The proposed net-work is based on a dual-net concentrated mesh, where 2 physical networks are implemented forprocessing different messages and improve throughput. A diagonal interconnection is used in thecentral part of the network for alleviating the traffic hot spot without significant hardware over-head. We evaluate the proposed design with synthetic traffic and real applications by using asimulator. Results indicate that,onaverage for 8 applications,thenetworklatency of the proposeddesign has reduced by 32% compared with regular mesh. Concerning efficiency when executingapplications, the average energy delay product of the proposed design is 52.7% and 29.7% betterthan mesh and concentrate mesh, respectively.