A1 Refereed original research article in a scientific journal
Hardware Trojan Mitigation Technique in Network-on-Chip (NoC)
Authors: Hussain Musharraf, Baloach Naveed Khan, Ali Gauhar, ElAffendi Mohammed, Ben Dhaou Imed, Ullah Syed Sajid, Uddin Mueen
Publisher: MDPI
Publication year: 2023
Journal: Micromachines
Journal name in source: MICROMACHINES
Journal acronym: MICROMACHINES-BASEL
Article number: 828
Volume: 14
Issue: 4
Number of pages: 19
DOI: https://doi.org/10.3390/mi14040828
Web address : https://www.mdpi.com/2072-666X/14/4/828
Self-archived copy’s web address: https://research.utu.fi/converis/portal/detail/Publication/179711777
Due to globalization in the semiconductor industry, malevolent modifications made in the hardware circuitry, known as hardware Trojans (HTs), have rendered the security of the chip very critical. Over the years, many methods have been proposed to detect and mitigate these HTs in general integrated circuits. However, insufficient effort has been made for hardware Trojans (HTs) in the network-on-chip. In this study, we implement a countermeasure to congeal the network-on-chip hardware design in order to prevent changes from being made to the network-on-chip design. We propose a collaborative method which uses flit integrity and dynamic flit permutation to eliminate the hardware Trojan inserted into the router of the NoC by a disloyal employee or a third-party vendor corporation. The proposed method increases the number of received packets by up to 10% more compared to existing techniques, which contain HTs in the destination address of the flit. Compared to the runtime HT mitigation method, the proposed scheme also decreases the average latency for the hardware Trojan inserted in the flit's header, tail, and destination field up to 14.7%, 8%, and 3%, respectively.
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