Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects

: Lehtonen T, Wolpert D, Liljeberg P, Plosila J, Ampadu P

Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

: 2010

: IEEE Transactions on Very Large Scale Integration (VLSI) Systems

: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

: IEEE T VLSI SYST

: 4

: 18

: 4

: 527

: 540

: 14

: 1063-8210

DOI: https://doi.org/10.1109/TVLSI.2009.2013711

We present a self-contained adaptive system for detecting and bypassing permanent errors in on-chip interconnects. The proposed system reroutes data on erroneous links to a set of spare wires without interrupting the data flow. To detect permanent errors at runtime, a novel in-line test (ILT) method using spare wires and a test pattern generator is proposed. In addition, an improved syndrome storing-based detection (SSD) method is presented and compared to the ILT method. Each detection method (ILT and SSD) is integrated individually into the noninterrupting adaptive system, and a case study is performed to compare them with Hamming and Bose-Chaudhuri-Hocquenghem (BCH) code implementations. In the presence of permanent errors, the probability of correct transmission in the proposed systems is improved by up to 140% over the standalone Hamming code. Furthermore, our methods achieve up to 38% area, 64% energy, and 61% latency improvements over the BCH implementation at comparable error performance.