A1 Refereed original research article in a scientific journal
Exploration of Temperature- Aware Placement Approaches in 2D and 3D Stacked Systems
Authors: Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila
Publisher: IGI global
Publication year: 2013
Journal: International Journal of Adaptive, Resilient and Autonomic Systems
Number in series: 3
Volume: 4
Issue: 3
First page : 61
Last page: 81
Number of pages: 21
ISSN: 1947-9220
DOI: https://doi.org/10.4018/jaras.2013070104
Web address : http://dx.doi.org/10.4018/jaras.2013070104
Abstract
Technology scaling has brought about dramatic rises in the on-chip power density of modern microprocessors. This has led to greater scrutiny and awareness of thermal management techniques which allows to uphold the thermal integrity of the chip. Higher temperatures or uneven distribution of temperatures result in timing uncertainties which induces performance and reliability concerns for the system. Future thermal problems would include 3D circuits. Three-dimensional technology offers greater device integration, reduced signal delay and reduced interconnect power. It also provides greater design flexibility by allowing heterogeneous integration. However, 3D technology also exacerbates the on-chip thermal issues and increases packaging and cooling costs. In order to resolve these issues, and avoid high and uneven temperatures, accurate thermal modeling and analysis, and thermal-aware placement optimizations are essential before tapeout. This paper presents an exploration of temperature-aware placement approaches in both the 2D and 3D stacked systems. Various thermal models were developed to investigate the effect of uniform power distribution, thermal-aware placement in 2D chips and 3D stacked systems on the thermal performance of the system thereby providing with metrics which can be used for thermal-aware mapping.
Technology scaling has brought about dramatic rises in the on-chip power density of modern microprocessors. This has led to greater scrutiny and awareness of thermal management techniques which allows to uphold the thermal integrity of the chip. Higher temperatures or uneven distribution of temperatures result in timing uncertainties which induces performance and reliability concerns for the system. Future thermal problems would include 3D circuits. Three-dimensional technology offers greater device integration, reduced signal delay and reduced interconnect power. It also provides greater design flexibility by allowing heterogeneous integration. However, 3D technology also exacerbates the on-chip thermal issues and increases packaging and cooling costs. In order to resolve these issues, and avoid high and uneven temperatures, accurate thermal modeling and analysis, and thermal-aware placement optimizations are essential before tapeout. This paper presents an exploration of temperature-aware placement approaches in both the 2D and 3D stacked systems. Various thermal models were developed to investigate the effect of uniform power distribution, thermal-aware placement in 2D chips and 3D stacked systems on the thermal performance of the system thereby providing with metrics which can be used for thermal-aware mapping.
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