In this paper, we propose a parameterized crypto co-processor based on Advanced Encryption Standard (AES). This parameterized AES module is integrated into a 32-bit general purpose 5-stage pipelined MIPS processor. The integrated AES module is a fully pipelined which follows both inner and outer round pipeline design. The processor fetch an instruction from the instruction memory and sends it to the decode stage. The crypto instruction pushed into the AES module during the decode stage, however if the instructions belongs to the MIPS processor it completes the remaining cycles on the pipeline stages of the MIPS processor. The parameterized AES module can achieve different latencies on different rounds of AES according to the application requirements. The effects of different number of rounds on latency, memory, and area are studied and reported.