Tero Säntti
D.Sc. (Tech.)
teansa@utu.fi Joukahaisenkatu 3-5 Turku |
FPGA, Space, Imaging, Radiation, Embedded Systems
D.Sc. (Tech.) in 2008, Microelectronics.
In addition to University stuff, I am also working in industry:
- Aboa Space Research Oy, Senior Engineer, Chairman of the Board
- Kovilta Oy, Lead FPGA Architect
All things related to FPGAs, and especially their use in space and/or in imaging.
- 2010 - 2012, FPGA Prototyping, (5 ECTS)
- 2009 - 2011 Sulautetut prosessorijärjestelmät (Embedded Processor Systems), (5 ECTS)
- 2005 - 2008 Mikroprosessoripohjaiset järjestelmät (Microprocessor Based Systems), (5 ECTS)
- 2007 Embedded Virtual Machines on FPGAs (6 / 3 ECTS), post-graduate level course
- 2006 Special Course on Floating Point Arithmetics, (3 ECTS)
- 2006 Special Course on External Funding, (2 ECTS)
Besides these, I have been participating in teaching of courses in electronics and related fields since 1998, first at Department of Applied Physics and later at Department of Information Technology, both in University of Turku. Most of these have been demonstrations and exercises. Courses include: Microprocessors, Digital Teaching Media, Analog Electronics II, Design of Electronic Equipment, Analog Electronics I, Multimedia Algorithms, LSI Circuit Design, Circuit Theory I and Basic Electronics.
2 of 2
- Seam Tracking with Adaptive Image Capture for Fine-tuning of a High Power Laser Welding Process (2015)
- International Conference on Machine Vision
- Electronics for the RADMON Instrument on the Aalto-l Student Satellite (2014) European Workshop on Microelectronics Education J Peltonen, H-P Hedman, A Ilmanen, M Lindroos, M Määttänen, J Pesonen, R Punkkinen, A Punkkinen, R Vainio, E Valtonen, T Säntti, J Pentikäinen, E Haeggström
- Line detection on FPGA with parallel sensor-level segmentation (2014)
- International Workshop on Cellular Nanoscale Networks and their Applications
- Spatter Tracking in Laser- and Manual Arc Welding with Sensor-level Pre-processing (2014) WSCG 2014 Olli Lahdenoja, Tero Säntti, Mika Laiho, Jonne Poikonen
- Characterizing spatters in laser welding of thick steel using motion flow analysis (2013)
- Lecture Notes in Computer Science
- Mapping multiple applications with unbounded and bounded number of cores on many-core networks-on-chip (2013)
- Microprocessors and Microsystems
- Parameter-Optimized Simulated Annealing for Application Mapping on Networks-on-Chip (2012) Yang Bo, Guang Liang, Säntti Tero, Plosila Juha
- Radmon – Radiaton monitor for Aalto-1 nanosatellite (2012) Physics Days 2012, Joensuu The 46th annual meeting of the Finnish Physical Society R Vainio, H-P Hedman, E Hæggström, J Peltonen, R Punkkinen, T Säntti, E Valtonen, A Ilmanen, M Mera, J Pentikäinen, J Perälä, J Sandhu, T Soukka
- t(k)-SA: Accelerated Simulated Annealing Algorithm for Application Mapping on Networks-on-Chip (2012) Genetic and Evolutionary Computation Conference (GECCO 2012) Yang B, Guang L, Santti T, Plosila J
- Tree-Model Based Contention-Aware Task Mapping on Many-Core Networks-on-Chip (2012) Yang Bo, Guang Liang, Säntti Tero, Plosila Juha
- Tree-Model Based Contention-Aware Task Mapping on Many-Core Network-on-Chips. (2011) IEEE Yang Bo, Guang Liang, Säntti Tero, Plosila Juha
- A Dynamic Fault-Tolerant Remapping Algorithm Based on Tree-Model of Network-on-Chip (2010)
- Proceedings : Design, Automation, and Test in Europe Conference and Exhibition
- An Improved Hardware Acceleration Scheme for Java Method Calls (2010) Norchip 2010 Säntti T, Tyystjärvi J, Plosila J
- Efficient Bytecode Optimizations for a Multicore Java Co-Processor System (2010) 2010 12th Biennial Baltic Electronics Conference (BEC2010) Tyystjärvi J, Säntti T, Plosila J
- Heap Access Optimizations for a Hardware-Accelerated Java Virtual Machine (2010) 2010 International Symposium on System-on-Chip Tyystjärvi J, Säntti T, Plosila J
- Multi-Application Mapping Algorithm for Network-on-Chip Platforms (2010) Proc. of the 26th IEEE Convention of Electrical and Electronics Engineers in Israel (IEEEI) Yang B, Guang L, Xu T C, Säntti T, Plosila J
- Multi-Application Multi-Step Mapping Method for Many-Core Network-on-Chips Platforms (2010) Proc. of the 28th IEEE Norchip Conference (NORCHIP 2010) Yang B, Guang L, Xu T C, Yin A W, Säntti T, Plosila J
- Parallel Performance Evaluation of a Multicore Java Co-Processor System (2010) "DATE 2010 Workshop ""Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications""" Tyystjärvi J, Säntti T, Plosila J
- Tree-Model Based Mapping for Energy-Efficient and Low-Latency Network-on-Chip (2010) Proceedings of 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Yang B, Xu T C, Säntti T, Plosila J
UTU Research Portal