Tree-Model Based Mapping for Energy-Efficient and Low-Latency Network-on-Chip

: Yang B, Xu T C, Säntti T, Plosila J

: 2010

: Proceedings of 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)

: 189

: 192

: 978-1-4244-6612-2

DOI: https://doi.org/10.1109/DDECS.2010.5491789