Juha Plosila
Head of the Robotics and Autonomous Systems Unit
juplos@utu.fi +358 29 450 2621 +358 50 383 9453 Vesilinnantie 5 Turku ORCID-tunniste: https://orcid.org/0000-0003-4018-5495 |
autonomous systems; robotics; unmanned vehicles; drones; embedded systems; cyber physical systems; internet of things; smart systems; fog/edge computing; multi-agent systems; multiprocessors; network on chip; system on chip; multiprocessor system on chip; chip multiprocessors; heterogeneous systems; reconfigurable computing; digital circuits and systems; formal methods
Autonomous Systems Laboratory (ASL): https://asl.utu.fi/
Dr. Juha Plosila (born 1965) is Professor (full) in autonomous systems and robotics and the head of the Autonomous Systems Laboratory (ASL) research group (https://asl.utu.fi/) and Smart Systems (formerly Embedded Electronics) cost centre at the University of Turku (UTU) Department of Computing (formerly Department of Future Technologies) since 2019. He received his PhD in electronics and communication technology from UTU in 1999 and his Adjunct Professor (Docent) title in digital systems design in 2006. He held a 5-year position of Academy Research Fellow (Academy of Finland) in 2006-2011 and served as a senior University Lecturer in embedded computing at UTU in 2011-2018. During his tenure at UTU since 2000, he has led many externally funded research projects, supervised more than 20 PhD theses, and served in the management committees of several master's programmes. Plosila has been an active participant in the European Institute of Innovation and Technology (EIT) knowledge and innovation community EIT Digital since 2011, leading the EIT Digital Master Programme in Embedded Systems (a European double-degree programme with 6 partner universities) and representing UTU in the EIT Digital Finland Node Strategy Committee.
Plosila's current research interests include intelligent adaptive and reconfigurable multi-processing platforms, self-aware multi-agent monitoring and control, machine-learning and optimization, as well as application of heterogeneous energy efficient architectures to new computational challenges in the areas of cyber-physical systems and internet-of-things, with a special focus on autonomous multi-robot systems and fog/edge computing. He also has a strong background in network-on-chip design and formal mehods for system design and verification.
Google Scholar statistics: https://scholar.google.com/citations?user=em4kCrUAAAAJ&hl=en
Lecturer for 18 different courses since 1999 in the fields of digital circuit and system design, multiprocessor architectures, computer architectures, reconfigurable computing, embedded systems, modelling and verification, as well as autonomous systems:
Autonomous Systems Architectures, MSc-level, 5 ECTS (2019- ); Regonfigurable Computing, MSc-level, 5 ECTS (at Fudan University, China, 2013- ); Processor Architectures, BSc-level, 5 ECTS (2020); Computer Architectures and Operating Systems, BSc-level, 4 ECTS (2017-2019), Multiprocessor Architectures, MSc-level, 5 ECTS, (2006, -08, -10, 2012-2018); System on Chip Design, MSc-level, 5 ECTS (2015-2016); Seminar on Embedded Computing, MSc/PhD-level, 5 ECTS (2012-2014); Modelling Parallel Systems, MSc-level (2011); Formal System Modelling and Verification, MSc-level, 5 ECTS, (2008, -10); Post Graduate Course on Digital Circuit & System Design, PhD-level; 5 ECTS (2009); Advanced Multiprocessor Systems, MSc-level, 5 ECTS (2009); System Verification, MSc-level, 5 ECTS (2007); Computer Architectures, BSc-level, 7 ECTS (2006-2007); Asynchronous System Design, MSc-level, 5 ECTS (2003, -05, -07); Formal System Specification and Design, MSc-level; 10 ECTS (2004, -06); Digital Integrated Circuit Design, BSc-level, 7 ECTS (2000-2005); Digital Systems Engineering, MSc-level, 10 ECTS (2001, -02, -04); Principles of Digital Design, BSc-level, 5 ECTS (1999-2000, -04).
- Memory-Efficient On-Chip Network with Adaptive Interfaces (2012)
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
(A1 Vertaisarvioitu alkuperäisartikkeli tieteellisessä lehdessä ) - Parameter-Optimized Simulated Annealing for Application Mapping on Networks-on-Chip (2012) Yang Bo, Guang Liang, Säntti Tero, Plosila Juha
(A4 Vertaisarvioitu artikkeli konferenssijulkaisussa) - PARS - An Efficient Congestion-Aware Routing Method for Networks-on-Chip (2012) Chang Xia, Ebrahimi Masoumeh, Daneshtalab Masoud, Westerlund Tomi, Plosila Juha
(A4 Vertaisarvioitu artikkeli konferenssijulkaisussa) - Partial-LastZ: An Optimized Hybridization Technique for 3D NoC Architecture Enabling Adaptive Inter-Layer Communication (2012) Rahmani Amir-Mohammad, Liljeberg Pasi, Plosila Juha, Man Ka Lok, Youngmin Kim, Tenhunen Hannu
(A4 Vertaisarvioitu artikkeli konferenssijulkaisussa) - Power and Thermal Analysis of Stacked Mesh 3D NoC Using AdaptiveXYZ Routing Algorithm (2012)
- Digital System Design
(A4 Vertaisarvioitu artikkeli konferenssijulkaisussa) - Semi-Serial On-Chip Link Implementation for Energy Efficiency and High Throughput (2012)
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
(A1 Vertaisarvioitu alkuperäisartikkeli tieteellisessä lehdessä ) - Status data and communication aspects in dynamically clustered network-on-chip monitoring (2012)
- Journal of Electrical and Computer Engineering
(A1 Vertaisarvioitu alkuperäisartikkeli tieteellisessä lehdessä ) - Survey of Self-Adaptive NoCs with Energy-Efficiency and Dependability (2012)
- International Journal of Embedded and Real-Time Communication Systems
(A2 Vertaisarvioitu katsausartikkeli tieteellisessä lehdessä) - t(k)-SA: Accelerated Simulated Annealing Algorithm for Application Mapping on Networks-on-Chip (2012) Genetic and Evolutionary Computation Conference (GECCO 2012) Yang B, Guang L, Santti T, Plosila J
(A4 Vertaisarvioitu artikkeli konferenssijulkaisussa) - Transport layer aware design of network interface in many-core systems (2012) Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2012 7th International Workshop on Fattah M, Daneshtalab M, Liljeberg P, Plosila J
(A4 Vertaisarvioitu artikkeli konferenssijulkaisussa) - Tree-Model Based Contention-Aware Task Mapping on Many-Core Networks-on-Chip (2012) Yang Bo, Guang Liang, Säntti Tero, Plosila Juha
(A1 Vertaisarvioitu alkuperäisartikkeli tieteellisessä lehdessä ) - Vertical and Horizontal Integration Towards Collective Adaptive System - a Visionary Approach (2012) Guang Liang, Nigussie Ethiopia, Plosila Juha, Tenhunen Hannu
(A4 Vertaisarvioitu artikkeli konferenssijulkaisussa) - A Fault-Tolerant and Hierarchical Routing Algorithm for NoC Architectures (2011) Mojtaba Valinataj, Pasi Liljeberg, Juha Plosila
(A4 Vertaisarvioitu artikkeli konferenssijulkaisussa) - Agent-based on-chip network using efficient selection method (2011) Ebrahimi Masoumeh, Daneshtalab Masoud, Liljeberg Pasi, Plosila Juha, Tenhunen Hannu
(A4 Vertaisarvioitu artikkeli konferenssijulkaisussa) - An adaptive fuzzy logic-based routing algorithm for networks-on-chip (2011) Dehyadegari Masoud, Daneshtalab Masoud, Ebrahimi Masoumeh, Plosila Juha, Mohammadi Siamak
(A4 Vertaisarvioitu artikkeli konferenssijulkaisussa) - Analysis of Monitoring Structures for Network-on-Chip: A Distributed Approach (2011)
- International Journal of Embedded and Real-Time Communication Systems
(A1 Vertaisarvioitu alkuperäisartikkeli tieteellisessä lehdessä ) - Analysis of Status Data Update in Dynamically Clustered Network-on-Chip Monitoring (2011) Ville Rantala, Teijo Lehtonen, Pasi Liljeberg, Juha Plosila
(A4 Vertaisarvioitu artikkeli konferenssijulkaisussa) - A reconfigurable and adaptive routing method for fault-tolerant mesh-based networks-on-chip (2011)
- AEU international journal of electronics and communication
(A1 Vertaisarvioitu alkuperäisartikkeli tieteellisessä lehdessä ) - A Stacked Mesh 3D NoC Architecture Enabling Congestion-Aware and Reliable Inter-Layer Communication (2011)
- Proceedings: Euromicro Workshop on Parallel and Distributed Processing
(A4 Vertaisarvioitu artikkeli konferenssijulkaisussa) - Boosting Performance of Self-Timed Delay-Insensitive Bit Parallel On-Chip Interconnects (2011)
- IET Circuits, Devices and Systems
(A1 Vertaisarvioitu alkuperäisartikkeli tieteellisessä lehdessä )