A4 Refereed article in a conference publication
Delay-insensitive on-chip communication link using low-swing simultaneous bidirectional signaling
Authors: Nigussie E, Plosila J, Isoaho J
Editors: Jürgen Becker, Andreas Herkersdorf, Amar Mukherjee, Asim Smailagic
Conference name: IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Publication year: 2006
Book title : Proceedings: IEEE Computer Society Annual Sysmposium on VLSI 2006: Emerging VLSI Technologies and Architectures
Journal name in source: IEEE Computer Society Annual Symposium on VLSI, Proceedings
First page : 217
Last page: 222
Number of pages: 2
ISBN: 0-7695-2533-4
DOI: https://doi.org/10.1109/ISVLSI.2006.34
Self-archived copy’s web address: http://research.utu.fi/converis/portal/Publication/17124297
In this paper we present the circuit implementation of a new asynchronous delay-insensitive on-chip link structure, where two modules placed on the opposite sides of the link can exchange data simultaneously. Unlike the conventional delay-insensitive dual-rail link which requires 2N + 1 interconnects to transfer N-data bit, N + 1 interconnects are required in this design. As two transceivers can access simultaneously the same physical interconnect the number of required interconnects halves compared to bidirectional transfer based on two separate unidirectional dual-rail links. This makes the link cost effective for future SoC The transceiver circuits are designed using multiple-valued current-mode logic, linear summation is implemented by wiring without active devices simplifying the resulting circuitry. By using 110 mV voltage swing the power consumption of the link is 8.32 mW for 689ps propagation delay and 5mm interconnect length. Some of the potential application areas of this link are between locally clocked modules in GALS system, between routers of NoC nodes, and in adaptive and reeonfigurable system where feedback information is crucial. The circuit is designed and simulated using Cadence Analog Spectre with 0.13 mu m CMOS technology.
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