A4 Article in conference proceedings

A 0.4-0.9V, 2.87pJ/cycle Near-Threshold ARM Cortex-M3 CPU with In-Situ Monitoring and Adaptive-Logic Scan




List of Authors: Hiienkari Markus, Gupta Navneet, Teittinen Jukka, Simonsson Jesse, Turnquist Matthew, Eriksson Jonas, Anttila Risto, Myllynen Ohto, Rämäkkö Hannu, Mäkikyrö Sofia, Koskinen Lauri

Conference name: IEEE Symposium on Low-Power and High-Speed Chips and Systems

Publication year: 2020

Journal: Proceedings for IEEE COOL Chips

Book title *: 2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)

Journal name in source: 2020 IEEE COOL CHIPS 23: IEEE SYMPOSIUM ON LOW-POWER AND HIGH-SPEED CHIPS AND SYSTEMS

Journal acronym: PROC IEEE COOL CHIPS

Title of series: Proceedings for IEEE COOL Chips

Volume number: 23

Number of pages: 3

ISBN: 978-1-7281-6348-2

eISBN: 978-1-7281-6347-5

ISSN: 2167-9657

DOI: http://dx.doi.org/10.1109/COOLCHIPS49199.2020.9097634


Abstract
An adaptive ARM Cortex-M3 with near-threshold to nominal voltage operation is presented. Using in-situ monitoring technology, the CPU energy is minimized across process, voltage, temperature, and applications. At the Minimum-Energy Point (MEP), the CPU achieves 2.87pJ/cycle (7.8MHz/0.378V). Absolute energy consumption is reduced by 76% by operating at the MEP. The core includes a novel configuration of industry-standard ATPG-compatible DFT architecture for adaptive logic testing and the system includes Dynamic Voltage and Frequency Scaling software. Additionally presented is an execution-frequency analysis algorithm based on software execution trace. The algorithm achieves 60% energy savings for an industry-standard speech-recognition software without any penalty in application throughput.


Last updated on 2021-16-09 at 10:21