An Adaptive, Low Restrictive and Fault Resilient Routing Algorithm for 3D Network-on-Chip - UTU Research Portal

A4 Refereed article in a conference publication

An Adaptive, Low Restrictive and Fault Resilient Routing Algorithm for 3D Network-on-Chip

Authors: Salamat R, Ebrahimi M, Bagherzadeh N

Editors: Daneshtalab M, Aldinucci M, Leppanen V, Lilius J, Brorsson M

Conference name: Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)

Publication year: 2015

Book title : 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)

Journal name in source: 23RD EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, AND NETWORK-BASED PROCESSING (PDP 2015)

First page : 392

Last page: 395

Number of pages: 4

ISBN: 978-1-4799-8491-6

ISSN: 1066-6192

DOI: https://doi.org/10.1109/PDP.2015.91

Abstract

The cost and reliability issues of TSVs move 3D-NoCs toward heterogonous designs with limited number of TSVs. However, designing a deadlock-free routing algorithm for such heterogonous architectures is extremely challenging due to the increased possibilities of forming cycles between and within layers for 3D designs. In this paper, we target designing a routing algorithm for heterogeneous 3D-NoCs with the capability of working under the technical limit in which there is just one TSV in the network. This algorithm is light-weight and provides adaptivity by using only one virtual channel along the Y dimension.