A4 Refereed article in a conference publication
Implementation and Analysis of Block Dense Matrix Decomposition on Network-on-Chips
Authors: Xu TC, Pahikkala T, Airola A, Liljeberg P, Plosila J, Salakoski T, Tenhunen H
Conference name: International Conference on High Performance Computing and Communication
Publication year: 2012
Book title : 2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems
Journal name in source: 2012 IEEE 14TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS & 2012 IEEE 9TH INTERNATIONAL CONFERENCE ON EMBEDDED SOFTWARE AND SYSTEMS (HPCC-ICESS)
First page : 516
Last page: 523
Number of pages: 8
ISBN: 978-1-4673-2164-8
ISSN: 2576-3504
DOI: https://doi.org/10.1109/HPCC.2012.76
The decomposition of a dense matrix into lower and upper triangular matrices is an important linear algebra kernel that used in scientific and engineering applications. To decompose large matrices efficiently, the matrix is divided into sub-matrices as blocks. The block matrix decomposition is introduced for parallel hardware platforms, e.g. supercomputers, multicore processors and GPIs. Recently, the Network-on-Chip (NoC) paradigm is proposed as a promising multicore architecture for future Chip Multiprocessors (CMPs) with hundreds or even thousands of cores. The communication bottleneck of traditional bus or crossbar based on-chip interconnect is alleviated in the NoC architecture. However, the implementation and analysis of parallel block matrix decomposition algorithm is implemented on the NoC platform. Evaluation results are presented using a cycle accurate full system simulator. We achieve parallel efficiency of 74.8% with a 64-node NoC, which outperforms other three multiprocessor systems (30.5%, 67% and 50% respectively). We also analyzed the impact of block size, cache behavior and network pressure of the platform.
