Effects of Back-Gate Bias on Switched-Capacitor DC-DC Converters in UTBB FD-SOI



: Matthew J. Turnquist, Guerric de Streel, David Bol, Markus Hiienkari, Lauri Koskinen

: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference

: 2014

: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference

: 2

: 978-1-4799-7439-9

DOI: https://doi.org/10.1109/S3S.2014.7028200


This paper explores the effects of back-gate bias on switched-capacitor (SC) DC-DC converters in 28 nm UTBB FD-SOI. By using back-gate bias to optimize the control circuitry and switches, the SC converter can operate with a peak efficiency of 72% in sleep mode (100 nW load) and 83% in active mode (100 μW load).




Last updated on 2024-26-11 at 19:04