Parallel Applications and On-chip Traffic Distributions: Observation, Implication and Modelling




Thomas Canhao Xu, Jonne Pohjankukka, Paavo Nevalainen, Ville Leppänen, Tapio Pahikkala

International Conference on Software Engineering and Applications

2015

Proceedings of the 10th International Conference on Software Engineering and Applications (ICSOFT-EA)

1

443

449

7

978-989-758-114-4

DOIhttps://doi.org/10.5220/0005553604430449



We study the traffic characteristics of parallel and high performance computing applications in this paper. Applications that utilize multiple cores are more and more common nowadays due to the emergence of multicore processors. However the design nature of single-threaded applications and multi-threaded applications can vary significantly. Furthermore the on-chip communication profile of multicore systems should be analysed and modelled for characterization and simulation purposes. We investigate several applications running on a full system simulation environment. The on-chip communication traces are gathered and analysed. We study the detailed low-level profiles of these applications. The applications are categorized into different groups according to various parallel programming paradigms. We discover that the trace data follow different parameters of power-law model. The problem is solved by applying least-squares linear regression. We propose a generic synthetic traffic model based on the analysis results.



Last updated on 2024-26-11 at 18:53