FPGA Implementation of AES-based Crypto Processor




Anwar H, Daneshtalab M, Ebrahimi M, Plosila J, Tenhunen H

IEEE international conference on electronics, circuits, and systems

PublisherIEEE

NEW YORK; 345 E 47TH ST, NEW YORK, NY 10017 USA

2013

IEEE International Symposium on Circuits and Systems. Proceedings

2013 Ieee 20th International Conference on Electronics, Circuits, and Systems (Icecs)

369

372

9781479924516



Increased demand for data security is an undeniable fact. Towards achieving higher security, cryptographic algorithms play an important role in the protection of data from unapproved usage. In this paper, we present a crypto processor using Advanced Encryption Standard (AES). The AES is integrated with a 32-bit general purpose 5-stage pipelined MIPS processor. The integrated AES module is a fully pipelined module which follows inner round and outer round pipeline design. The results show that the presented pipeline version of the AES algorithm along with MIPS processor outperforms traditional methods. At the operating frequency of 553 MHz, the proposed design can achieve the throughput of 58 Gbps, the latency of 240 ns, and the minimum power consumption of 76 mw.




Last updated on 2024-26-11 at 14:11