A1 Refereed original research article in a scientific journal
Design and Implementation of Reconfigurable FIFOs for Voltage/Frequency Island-Based Networks-on-Chip
Authors: Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen
Publisher: Elsevier
Publication year: 2013
Journal: Microprocessors and Microsystems
Journal acronym: MICPRO
Number in series: 4-5
Volume: 37
Issue: 4-5
First page : 432
Last page: 445
Number of pages: 14
ISSN: 0141-9331
DOI: https://doi.org/10.1016/j.micpro.2012.07.003
Abstract
One of the major design bottlenecks in today’s high-performance VLSI systems is the distribution of a single global clock across a chip due to process variability, power dissipation, and multi-cycle cross-chip signaling. A Network-on-Chip architecture partitioned into several Voltage/Frequency Islands (VFIs) is considered as a promising approach for achieving fine-grain system-level power management. In a VFI-based architecture, a clock is utilized for local data synchronization, while inter-island communication is handled asynchronously. To interface the islands on a chip, operating at different frequencies, a complex bi-synchronous FIFO design is inevitable. However, these FIFOs are not needed if adjacent switches belong to the same clock domain. In this paper, a Reconfigurable Synchronous/Bi-Synchronous (RSBS) FIFO is proposed which can adapt its operation to either synchronous or bi-synchronous mode. Four different scalable and synthesizable designs are presented. In addition, a technique is suggested to show how the FIFO could be utilized in a VFI-based NoC. Moreover, we present a mesochronous adaptation method and propose Reconfigurable Mesochronous/Bi-Synchronous (RMBS) FIFOs. Our extensive experiments reveal that compared to a non-reconfigurable system architecture, the proposed reconfigurable FIFOs can help to achieve up to 17% savings in the average power consumption of NoC switches and 29% improvement in the total average packet latency in the case of an MPEG-4 encoder application.
One of the major design bottlenecks in today’s high-performance VLSI systems is the distribution of a single global clock across a chip due to process variability, power dissipation, and multi-cycle cross-chip signaling. A Network-on-Chip architecture partitioned into several Voltage/Frequency Islands (VFIs) is considered as a promising approach for achieving fine-grain system-level power management. In a VFI-based architecture, a clock is utilized for local data synchronization, while inter-island communication is handled asynchronously. To interface the islands on a chip, operating at different frequencies, a complex bi-synchronous FIFO design is inevitable. However, these FIFOs are not needed if adjacent switches belong to the same clock domain. In this paper, a Reconfigurable Synchronous/Bi-Synchronous (RSBS) FIFO is proposed which can adapt its operation to either synchronous or bi-synchronous mode. Four different scalable and synthesizable designs are presented. In addition, a technique is suggested to show how the FIFO could be utilized in a VFI-based NoC. Moreover, we present a mesochronous adaptation method and propose Reconfigurable Mesochronous/Bi-Synchronous (RMBS) FIFOs. Our extensive experiments reveal that compared to a non-reconfigurable system architecture, the proposed reconfigurable FIFOs can help to achieve up to 17% savings in the average power consumption of NoC switches and 29% improvement in the total average packet latency in the case of an MPEG-4 encoder application.
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