A4 Vertaisarvioitu artikkeli konferenssijulkaisussa
Non-blocking BIST for continuous reliability monitoring of Networks-on-Chip
Tekijät: Wang J., Huang L., Ebrahimi M., Li Q., Li G., Jantsch A.
Toimittaja: Pamela Abshire, Ralph Etienne-Cummings
Konferenssin vakiintunut nimi: IEEE International Symposium on Circuits and Systems
Kustantaja: Institute of Electrical and Electronics Engineers Inc.
Julkaisuvuosi: 2017
Journal: IEEE International Symposium on Circuits and Systems. Proceedings
Kokoomateoksen nimi: 2017 IEEE International Symposium on Circuits and Systems (ISCAS)
Tietokannassa oleva lehden nimi: Proceedings - IEEE International Symposium on Circuits and Systems
Aloitussivu: 2158
Lopetussivu: 2161
Sivujen määrä: 4
ISBN: 978-1-5090-1427-9
eISBN: 978-1-4673-6853-7
ISSN: 0271-4302
DOI: https://doi.org/10.1109/ISCAS.2017.8050828
To achieve high reliability in on-chip networks, frequent runs of Built-in Self-Test allow the detection of and recovery from faults before they affect packets and the system functionality. However, to test routers, wrappers isolate cores from the network which leads to execution blocking and performance loss. In this paper, we propose a design-for-test reconfigurable router with two alternative bypassing channels. The router architecture allows maintaining the connection between cores and the network during the testing procedure by utilizing the bypassing channels. With the help of an adaptive routing algorithm and a testing strategy, networks can be fully tested at a high testing frequency with <15% increase of execution time. © 2017 IEEE.
