Fast thermopile readout circuit arrangement for array processors




Grönroos Mika, Nevalainen Tapani, Poikonen Jonne, Paasio Ari

No available

IEEE International Symposium on Circuits and Systems

2017

2017 IEEE International Symposium on Circuits and Systems (ISCAS)

1310

1314

5

978-1-5090-1427-9

978-1-4673-6853-7

0271-4302

DOIhttps://doi.org/10.1109/ISCAS.2017.8050591



The high speed thermal imaging is necessary in many applications.
However, the traditional column-wise readout implementations reduce the
achievable frame-rate. Also, the analog integration of each individual
pixel is not possible without sacrificing the pixel area. In this paper
we present an algorithm that can be used in parallel focal-plane
processing for fast imaging. First we prove that our method is valid in
the ideal case. Then we add non-idealities such as noise and show means
to cope with them.



Last updated on 2024-26-11 at 21:07