The possibilities to increase single-core performance have ended due to
limited instruction-level parallelism and a high penalty when increasing
frequency. This prompted designers to move toward multi-core paradigms [1], largely supported by transistor scaling [2].
Scaling down transistor gate length makes it possible to switch them
faster at a lower power, as they have a low capacitance. In this
context, an important consideration is power density—the
power dissipated per unit area. Dennard’s scaling establishes that
reducing physical parameters of transistors allows operating them at
lower voltage and thus at lower power, because power consumption is
proportional to the square of the applied voltage, keeping power density
constant [3]. Dennard’s estimation of scaling effects and constant power density is shown in Table 1.1.
Theoretically, scaling down further should result in more computational
capacity per unit area. However, scaling is reaching its physical
limits to an extent that voltage cannot be scaled down as much as
transistor gate length leading to failure of Dennardian trend. This
along with a rise in leakage current results in increased power density,
rather than a constant power density. Higher power density implies more
heat generated in a unit area and hence higher chip temperatures which
have to be dissipated through cooling solutions, as increase in
temperature beyond a certain level results in unreliable functionality,
faster aging, and even permanent failure of the chip. To ensure a safe
operation, it is essential for the chip to perform within a fixed power
budget [4].
In order to avoid too high power dissipation, a certain part of the
chip needs to remain inactive; the inactive part is termed dark silicon [5].
Hence, we have to operate working cores in a multi-core system at less
than their full capacity, limiting the performance, resource
utilization, and efficiency of the system.