Network on Chip (NoC) has been proposed as a solution for addressing the challenges in System on Chip (SoC) design. Designing a topology and its routing schemes are vital problems in a NoC. One of the major challenges that designers face today in 3D integration is how to route the data packets within a layer and across the layers in a scalable and efficient manner. In any 3D topology, minimizing the amount of data packet transmissions during the routing is still an open problem. Any efficient traditional routing schemes should avoid deadlocks and minimize network congestion from a source node to a destination node.

In this paper, we propose a 3D recursive hyper graph Hamiltonian connected network and we propose a deadlock free routing algorithm to minimize congestion in the network. We show that the proposed topology outperforms the topology presented by Dubois et al. (Elevator-First: a Dealock-free distributed routing algorithm for vertically partially connected 3d-Nocs, IEEE Trans. Comput. 62(3) (2013) 609–615)[1] with respect to average network latency. Also, we analysis the delay bound of the switches for the proposed topology and 3D Partially connected Mesh Topology (PMT) and conclude that our topology performs better than 3D PMT.