Vertaisarvioitu alkuperäisartikkeli tai data-artikkeli tieteellisessä aikakauslehdessä (A1)
A moving threads processor architecture MTPA
Julkaisun tekijät: Forsell M, Leppänen V
Kustantaja: SPRINGER
Julkaisuvuosi: 2011
Journal: Journal of Supercomputing
Tietokannassa oleva lehden nimi: JOURNAL OF SUPERCOMPUTING
Lehden akronyymi: J SUPERCOMPUT
Numero sarjassa: 1
Volyymi: 57
Julkaisunumero: 1
Aloitussivu: 5
Lopetussivun numero: 19
Sivujen määrä: 15
ISSN: 0920-8542
DOI: http://dx.doi.org/10.1007/s11227-011-0573-9
Tiivistelmä
Moving threads is a new kind of approach for multicore processor architectures. Traditionally, each thread stays in the core where it is created, and data is moved from the main memory via caches to each core and thread. In the moving threads approach, each core can access only a certain portion of the main memory via its local memory block, and thus extremely lightweight threads are moved between the cores. As a consequence, all kinds of cache coherence problems and need for read reply messages are eliminated. Also Lamport's sequential consistency of shared memory multiprocessor systems is achieved for free. In this paper, we propose a processor architecture (MTPA) for the moving threads paradigm. We describe the overall structure, operation, instruction set, and thread management mechanism as well as evaluate the proposed architecture with different functional unit settings with simulations and give early silicon area and power consumption estimates.
Moving threads is a new kind of approach for multicore processor architectures. Traditionally, each thread stays in the core where it is created, and data is moved from the main memory via caches to each core and thread. In the moving threads approach, each core can access only a certain portion of the main memory via its local memory block, and thus extremely lightweight threads are moved between the cores. As a consequence, all kinds of cache coherence problems and need for read reply messages are eliminated. Also Lamport's sequential consistency of shared memory multiprocessor systems is achieved for free. In this paper, we propose a processor architecture (MTPA) for the moving threads paradigm. We describe the overall structure, operation, instruction set, and thread management mechanism as well as evaluate the proposed architecture with different functional unit settings with simulations and give early silicon area and power consumption estimates.
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