A4 Refereed article in a conference publication
On Challenges for Implementing Pixelwise DA Converter in 3D
Authors: Paasio A, Ansio H
Publication year: 2012
Journal: International Workshop on Cellular Nanoscale Networks and their Applications
Book title : Cellular Nanoscale Networks and Their Applications (CNNA), 2012, Proceedings of the 13th International Workshop on
Journal name in source: 2012 13TH INTERNATIONAL WORKSHOP ON CELLULAR NANOSCALE NETWORKS AND THEIR APPLICATIONS (CNNA)
Journal acronym: INT WORK CELL NANO
Number of pages: 3
ISBN: 978-1-4673-0287-6
ISSN: 2165-0160
Abstract
Vision chips are natural candidates for being among the first areas that are able to utilize the emerging 3D integration possibilities. In some 2D vision chip architechtures there are pixel level AD and/or DA converters that are used for various purposes. This article covers the challenges and needs when targeting a megapixel architechture within a 1cm(2) chip area. The Through-Silicon-Vias (TSVs) on one hand allow the 3D integration, but on the other hand pose strict challenges for the design. The TSVs occupy certain area and in an area restricted design, the number of TSVs should be minimized. Also the associated Keep-Out-Zone (KOZ) for each TSV should be taken into account.
Vision chips are natural candidates for being among the first areas that are able to utilize the emerging 3D integration possibilities. In some 2D vision chip architechtures there are pixel level AD and/or DA converters that are used for various purposes. This article covers the challenges and needs when targeting a megapixel architechture within a 1cm(2) chip area. The Through-Silicon-Vias (TSVs) on one hand allow the 3D integration, but on the other hand pose strict challenges for the design. The TSVs occupy certain area and in an area restricted design, the number of TSVs should be minimized. Also the associated Keep-Out-Zone (KOZ) for each TSV should be taken into account.
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