A4 Refereed article in a conference publication
Ultra-Wide Voltage Range 32-bit RISC CPU with Timing-Error Prevention in 28nm CMOS
Authors: Markus Hiienkari, Jukka Teittinen, Lauri Koskinen, Matthew Turnquist, Mikko Kaltiokallio, Jani Mäkipää, Arto Rantala, Matti Sopanen
Conference name: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
Publication year: 2014
Book title : IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
Number of pages: 2
ISBN: 978-1-4799-7439-9
ISSN: 1078-621X
DOI: https://doi.org/10.1109/S3S.2014.7028192
To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS with wide range of adjustable voltage/frequency from 250mV/85kHz to 750mV/135MHz. The CPU employs timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing energy efficiency at a given operating point. Measurements show 3.15pJ/cyc energy consumption at 400mV, which corresponds to 39% energy savings and 83% EDP improvement compared to operation based on static signoff timing.
