Ultra Low-Power Array Processor Propagation Circuit Arrangement




Ari Paasio

International Symposium on Circuits and Systems

2016

2016 IEEE International Symposium on Circuits and Systems (ISCAS 2016)

2515

2518

4

978-1-4799-5342-4

978-1-4799-5341-7

0271-4302

DOIhttps://doi.org/10.1109/ISCAS.2016.7539104



Array processors, and vision chips in particular, have mostly been designed from maximum processing speed point of view. However, there are applications in e.g. surveillance field, where the image content is analyzed rather rarely and where on the other hand the power consumption is of greater importance due to battery operation functionality. One of the major building block in the array processor is the binary wave computing engine offering remarkable computing capabilities when the processing is performed asynchronously. In this paper, we propose a new propagating network offering extremely low power including leakage. The computing speed is much slower compared to nanosecond propagation speeds typically available in vision chips, but in low duty cycled operations this new approach may offer great advantages in power consumption. The network consists of PMOS transistors only and operates in subthreshold region. The principle of operation is demonstrated by a one dimensional propagation network offering initialization, propagation starting and propagation inhibition operations as well as propagation direction control similarly to the basic propagation networks.



Last updated on 2024-26-11 at 17:05