A4 Vertaisarvioitu artikkeli konferenssijulkaisussa
Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip Networks
Tekijät: Yin AW, Guang L, Nigussie E, Liljeberg P, Isoaho J, Tenhunen H
Konferenssin vakiintunut nimi: Euromicro Conference on Digital Systems Design, Architectures, Methods and Tools
Julkaisuvuosi: 2009
Kokoomateoksen nimi: 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Tietokannassa oleva lehden nimi: PROCEEDINGS OF THE 2009 12TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN, ARCHITECTURES, METHODS AND TOOLS
Aloitussivu: 141
Lopetussivu: 146
Sivujen määrä: 6
ISBN: 978-0-7695-3782-5
DOI: https://doi.org/10.1109/DSD.2009.197
Tiivistelmä
A feasible and scalable per-core DVFS architecture for on-chip network is presented. The supplies are dynamically adjusted at a very fine granularity based on the local traffic status. The adoption of multiple voltage supply networks and power selecting transistors provides the architecture with scalability and feasibility superior to existing similar techniques. With high-level simulation using 65nm power model obtained from widely-acknowledged tools, the effectiveness of the technique is demonstrated with quantitative analysis of energy overhead and latency penalty. Under various traffic patterns, the average flit energy is reduced considerably, ranging from 45% to 60%, with moderately increased but stable transmission latency.
A feasible and scalable per-core DVFS architecture for on-chip network is presented. The supplies are dynamically adjusted at a very fine granularity based on the local traffic status. The adoption of multiple voltage supply networks and power selecting transistors provides the architecture with scalability and feasibility superior to existing similar techniques. With high-level simulation using 65nm power model obtained from widely-acknowledged tools, the effectiveness of the technique is demonstrated with quantitative analysis of energy overhead and latency penalty. Under various traffic patterns, the average flit energy is reduced considerably, ranging from 45% to 60%, with moderately increased but stable transmission latency.
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