A4 Refereed article in a conference publication
Fault-Resilient Routing Unit in NoCs
Authors: Zhang XF, Ebrahimi M, Huang LT, Li GJ
Editors: Thomas Büchner,Danella Zhao, Karan Bhatia, Ramalingam Sridhar
Conference name: IEEE International System-on-Chip Conference
Publication year: 2015
Book title : 2015 28th IEEE International System-on-Chip Conference (SOCC)
Journal name in source: 2015 28TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC)
First page : 164
Last page: 169
Number of pages: 6
ISBN: 978-1-4673-9095-8
eISBN: 978-1-4673-9094-1
DOI: https://doi.org/10.1109/SOCC.2015.7406933
Abstract
With aggressive technology scaling in deep submicron era, burgeoning transistors make chips more susceptible to failures. It is inevitable that process variation is gradually becoming a crucial challenge in the IC design. In addition, aging leads to faults, shortening the lifetime of the circuits. Networks-on-chip also come to the problems caused by variations and aging, leading to degraded performance and erroneous behaviors. Faults may occur in numerous locations of the on-chip networks and once they occur in the control path, more severe effects such as deadlock and livelock are expected. In this paper, we present a fine-grained mechanism to tolerate faults in the routing computation units without disabling the faulty routers. By applying this mechanism, routing and packet-receiving services are separated. The faulty routing computation unit is replaced by a light-weight redundant circuit, providing static but reliable routing services. The other components in this router are still functional retaining the on-chip performance. Experimental results indicate that the on-chip network with the proposed mechanism is fault-tolerant when 14% of all routing computation modules are suffering from faults. The area overhead and power consumption of the proposed method is around 7.29% and 6.20% over the baseline approach.
With aggressive technology scaling in deep submicron era, burgeoning transistors make chips more susceptible to failures. It is inevitable that process variation is gradually becoming a crucial challenge in the IC design. In addition, aging leads to faults, shortening the lifetime of the circuits. Networks-on-chip also come to the problems caused by variations and aging, leading to degraded performance and erroneous behaviors. Faults may occur in numerous locations of the on-chip networks and once they occur in the control path, more severe effects such as deadlock and livelock are expected. In this paper, we present a fine-grained mechanism to tolerate faults in the routing computation units without disabling the faulty routers. By applying this mechanism, routing and packet-receiving services are separated. The faulty routing computation unit is replaced by a light-weight redundant circuit, providing static but reliable routing services. The other components in this router are still functional retaining the on-chip performance. Experimental results indicate that the on-chip network with the proposed mechanism is fault-tolerant when 14% of all routing computation modules are suffering from faults. The area overhead and power consumption of the proposed method is around 7.29% and 6.20% over the baseline approach.
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